Andrew Lunn 4b8f7a11c9 ARM: MM: Add DT binding for Feroceon L2 cache ... Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>		2014-02-22 20:43:49 +00:00
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asm	ARM: MM: Add DT binding for Feroceon L2 cache	2014-02-22 20:43:49 +00:00
debug	i.MX SoC changes for 3.14:	2014-01-02 12:10:12 -08:00
uapi/asm	First round of KVM updates for 3.14; PPC parts will come next week.	2014-01-22 21:40:43 -08:00