760 lines
22 KiB
C
760 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
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#include "dpu_encoder_phys.h"
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#include "dpu_hw_interrupts.h"
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#include "dpu_core_irq.h"
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#include "dpu_formats.h"
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#include "dpu_trace.h"
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#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
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(e) && (e)->parent ? \
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(e)->parent->base.id : -1, \
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(e) && (e)->hw_intf ? \
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(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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#define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
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(e) && (e)->parent ? \
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(e)->parent->base.id : -1, \
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(e) && (e)->hw_intf ? \
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(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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#define to_dpu_encoder_phys_vid(x) \
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container_of(x, struct dpu_encoder_phys_vid, base)
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static bool dpu_encoder_phys_vid_is_master(
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struct dpu_encoder_phys *phys_enc)
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{
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bool ret = false;
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if (phys_enc->split_role != ENC_ROLE_SLAVE)
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ret = true;
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return ret;
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}
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static void drm_mode_to_intf_timing_params(
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const struct dpu_encoder_phys *phys_enc,
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const struct drm_display_mode *mode,
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struct intf_timing_params *timing)
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{
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memset(timing, 0, sizeof(*timing));
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if ((mode->htotal < mode->hsync_end)
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|| (mode->hsync_start < mode->hdisplay)
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|| (mode->vtotal < mode->vsync_end)
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|| (mode->vsync_start < mode->vdisplay)
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|| (mode->hsync_end < mode->hsync_start)
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|| (mode->vsync_end < mode->vsync_start)) {
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DPU_ERROR(
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"invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
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mode->hsync_start, mode->hsync_end,
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mode->htotal, mode->hdisplay);
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DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
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mode->vsync_start, mode->vsync_end,
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mode->vtotal, mode->vdisplay);
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return;
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}
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/*
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* https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
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* Active Region Front Porch Sync Back Porch
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* <-----------------><------------><-----><----------->
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* <- [hv]display --->
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* <--------- [hv]sync_start ------>
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* <----------------- [hv]sync_end ------->
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* <---------------------------- [hv]total ------------->
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*/
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timing->width = mode->hdisplay; /* active width */
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timing->height = mode->vdisplay; /* active height */
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timing->xres = timing->width;
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timing->yres = timing->height;
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timing->h_back_porch = mode->htotal - mode->hsync_end;
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timing->h_front_porch = mode->hsync_start - mode->hdisplay;
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timing->v_back_porch = mode->vtotal - mode->vsync_end;
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timing->v_front_porch = mode->vsync_start - mode->vdisplay;
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timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
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timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
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timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
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timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
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timing->border_clr = 0;
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timing->underflow_clr = 0xff;
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timing->hsync_skew = mode->hskew;
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/* DSI controller cannot handle active-low sync signals. */
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if (phys_enc->hw_intf->cap->type == INTF_DSI) {
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timing->hsync_polarity = 0;
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timing->vsync_polarity = 0;
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}
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/*
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* For edp only:
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* DISPLAY_V_START = (VBP * HCYCLE) + HBP
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* DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
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*/
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/*
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* if (vid_enc->hw->cap->type == INTF_EDP) {
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* display_v_start += mode->htotal - mode->hsync_start;
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* display_v_end -= mode->hsync_start - mode->hdisplay;
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* }
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*/
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}
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static u32 get_horizontal_total(const struct intf_timing_params *timing)
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{
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u32 active = timing->xres;
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u32 inactive =
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timing->h_back_porch + timing->h_front_porch +
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timing->hsync_pulse_width;
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return active + inactive;
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}
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static u32 get_vertical_total(const struct intf_timing_params *timing)
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{
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u32 active = timing->yres;
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u32 inactive =
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timing->v_back_porch + timing->v_front_porch +
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timing->vsync_pulse_width;
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return active + inactive;
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}
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/*
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* programmable_fetch_get_num_lines:
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* Number of fetch lines in vertical front porch
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* @timing: Pointer to the intf timing information for the requested mode
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*
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* Returns the number of fetch lines in vertical front porch at which mdp
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* can start fetching the next frame.
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*
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* Number of needed prefetch lines is anything that cannot be absorbed in the
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* start of frame time (back porch + vsync pulse width).
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*
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* Some panels have very large VFP, however we only need a total number of
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* lines based on the chip worst case latencies.
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*/
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static u32 programmable_fetch_get_num_lines(
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struct dpu_encoder_phys *phys_enc,
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const struct intf_timing_params *timing)
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{
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u32 worst_case_needed_lines =
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phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
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u32 start_of_frame_lines =
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timing->v_back_porch + timing->vsync_pulse_width;
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u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
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u32 actual_vfp_lines = 0;
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/* Fetch must be outside active lines, otherwise undefined. */
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if (start_of_frame_lines >= worst_case_needed_lines) {
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DPU_DEBUG_VIDENC(phys_enc,
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"prog fetch is not needed, large vbp+vsw\n");
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actual_vfp_lines = 0;
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} else if (timing->v_front_porch < needed_vfp_lines) {
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/* Warn fetch needed, but not enough porch in panel config */
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pr_warn_once
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("low vbp+vfp may lead to perf issues in some cases\n");
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DPU_DEBUG_VIDENC(phys_enc,
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"less vfp than fetch req, using entire vfp\n");
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actual_vfp_lines = timing->v_front_porch;
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} else {
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DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
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actual_vfp_lines = needed_vfp_lines;
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}
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DPU_DEBUG_VIDENC(phys_enc,
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"v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
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timing->v_front_porch, timing->v_back_porch,
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timing->vsync_pulse_width);
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DPU_DEBUG_VIDENC(phys_enc,
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"wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
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worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
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return actual_vfp_lines;
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}
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/*
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* programmable_fetch_config: Programs HW to prefetch lines by offsetting
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* the start of fetch into the vertical front porch for cases where the
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* vsync pulse width and vertical back porch time is insufficient
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*
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* Gets # of lines to pre-fetch, then calculate VSYNC counter value.
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* HW layer requires VSYNC counter of first pixel of tgt VFP line.
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*
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* @timing: Pointer to the intf timing information for the requested mode
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*/
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static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
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const struct intf_timing_params *timing)
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{
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struct intf_prog_fetch f = { 0 };
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u32 vfp_fetch_lines = 0;
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u32 horiz_total = 0;
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u32 vert_total = 0;
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u32 vfp_fetch_start_vsync_counter = 0;
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unsigned long lock_flags;
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if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
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return;
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vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
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if (vfp_fetch_lines) {
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vert_total = get_vertical_total(timing);
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horiz_total = get_horizontal_total(timing);
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vfp_fetch_start_vsync_counter =
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(vert_total - vfp_fetch_lines) * horiz_total + 1;
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f.enable = 1;
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f.fetch_start = vfp_fetch_start_vsync_counter;
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}
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DPU_DEBUG_VIDENC(phys_enc,
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"vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
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vfp_fetch_lines, vfp_fetch_start_vsync_counter);
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spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
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phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
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spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
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}
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static bool dpu_encoder_phys_vid_mode_fixup(
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struct dpu_encoder_phys *phys_enc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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if (phys_enc)
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DPU_DEBUG_VIDENC(phys_enc, "\n");
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/*
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* Modifying mode has consequences when the mode comes back to us
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*/
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return true;
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}
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static void dpu_encoder_phys_vid_setup_timing_engine(
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struct dpu_encoder_phys *phys_enc)
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{
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struct drm_display_mode mode;
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struct intf_timing_params timing_params = { 0 };
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const struct dpu_format *fmt = NULL;
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u32 fmt_fourcc = DRM_FORMAT_RGB888;
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unsigned long lock_flags;
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struct dpu_hw_intf_cfg intf_cfg = { 0 };
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if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
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DPU_ERROR("invalid encoder %d\n", phys_enc != 0);
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return;
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}
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mode = phys_enc->cached_mode;
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if (!phys_enc->hw_intf->ops.setup_timing_gen) {
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DPU_ERROR("timing engine setup is not supported\n");
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return;
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}
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DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
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drm_mode_debug_printmodeline(&mode);
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if (phys_enc->split_role != ENC_ROLE_SOLO) {
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mode.hdisplay >>= 1;
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mode.htotal >>= 1;
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mode.hsync_start >>= 1;
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mode.hsync_end >>= 1;
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DPU_DEBUG_VIDENC(phys_enc,
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"split_role %d, halve horizontal %d %d %d %d\n",
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phys_enc->split_role,
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mode.hdisplay, mode.htotal,
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mode.hsync_start, mode.hsync_end);
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}
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drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
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fmt = dpu_get_dpu_format(fmt_fourcc);
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DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
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intf_cfg.intf = phys_enc->hw_intf->idx;
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intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
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intf_cfg.stream_sel = 0; /* Don't care value for video mode */
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intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
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spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
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phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
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&timing_params, fmt);
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phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
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spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
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programmable_fetch_config(phys_enc, &timing_params);
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}
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static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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struct dpu_hw_ctl *hw_ctl;
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unsigned long lock_flags;
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u32 flush_register = 0;
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int new_cnt = -1, old_cnt = -1;
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if (!phys_enc)
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return;
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hw_ctl = phys_enc->hw_ctl;
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if (!hw_ctl)
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return;
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DPU_ATRACE_BEGIN("vblank_irq");
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if (phys_enc->parent_ops->handle_vblank_virt)
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phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent,
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phys_enc);
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old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt);
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/*
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* only decrement the pending flush count if we've actually flushed
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* hardware. due to sw irq latency, vblank may have already happened
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* so we need to double-check with hw that it accepted the flush bits
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*/
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spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
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if (hw_ctl && hw_ctl->ops.get_flush_register)
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flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
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if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
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new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
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-1, 0);
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spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
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/* Signal any waiting atomic commit thread */
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wake_up_all(&phys_enc->pending_kickoff_wq);
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DPU_ATRACE_END("vblank_irq");
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}
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static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
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{
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struct dpu_encoder_phys *phys_enc = arg;
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if (!phys_enc)
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return;
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if (phys_enc->parent_ops->handle_underrun_virt)
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phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
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phys_enc);
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}
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static bool dpu_encoder_phys_vid_needs_single_flush(
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struct dpu_encoder_phys *phys_enc)
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{
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return phys_enc->split_role != ENC_ROLE_SOLO;
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}
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static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_encoder_irq *irq;
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/*
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* Initialize irq->hw_idx only when irq is not registered.
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* Prevent invalidating irq->irq_idx as modeset may be
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* called many times during dfps.
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*/
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irq = &phys_enc->irq[INTR_IDX_VSYNC];
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if (irq->irq_idx < 0)
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irq->hw_idx = phys_enc->intf_idx;
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irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
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if (irq->irq_idx < 0)
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irq->hw_idx = phys_enc->intf_idx;
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}
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static void dpu_encoder_phys_vid_mode_set(
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struct dpu_encoder_phys *phys_enc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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if (!phys_enc || !phys_enc->dpu_kms) {
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DPU_ERROR("invalid encoder/kms\n");
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return;
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}
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if (adj_mode) {
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phys_enc->cached_mode = *adj_mode;
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drm_mode_debug_printmodeline(adj_mode);
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DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
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}
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_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
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}
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static int dpu_encoder_phys_vid_control_vblank_irq(
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struct dpu_encoder_phys *phys_enc,
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bool enable)
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{
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int ret = 0;
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int refcount;
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if (!phys_enc) {
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DPU_ERROR("invalid encoder\n");
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return -EINVAL;
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}
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refcount = atomic_read(&phys_enc->vblank_refcount);
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/* Slave encoders don't report vblank */
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if (!dpu_encoder_phys_vid_is_master(phys_enc))
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goto end;
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/* protect against negative */
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if (!enable && refcount == 0) {
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ret = -EINVAL;
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goto end;
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}
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DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
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atomic_read(&phys_enc->vblank_refcount));
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if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
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ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
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else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
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ret = dpu_encoder_helper_unregister_irq(phys_enc,
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INTR_IDX_VSYNC);
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end:
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if (ret) {
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DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
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DRMID(phys_enc->parent),
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phys_enc->hw_intf->idx - INTF_0, ret, enable,
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refcount);
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}
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return ret;
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}
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static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_hw_ctl *ctl;
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u32 flush_mask = 0;
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ctl = phys_enc->hw_ctl;
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DPU_DEBUG_VIDENC(phys_enc, "\n");
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if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
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return;
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dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
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dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
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/*
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* For single flush cases (dual-ctl or pp-split), skip setting the
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* flush bit for the slave intf, since both intfs use same ctl
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* and HW will only flush the master.
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*/
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if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
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!dpu_encoder_phys_vid_is_master(phys_enc))
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goto skip_flush;
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ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
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ctl->ops.update_pending_flush(ctl, flush_mask);
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skip_flush:
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DPU_DEBUG_VIDENC(phys_enc,
|
|
"update pending flush ctl %d flush_mask %x\n",
|
|
ctl->idx - CTL_0, flush_mask);
|
|
|
|
/* ctl_flush & timing engine enable will be triggered by framework */
|
|
if (phys_enc->enable_state == DPU_ENC_DISABLED)
|
|
phys_enc->enable_state = DPU_ENC_ENABLING;
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
if (!phys_enc) {
|
|
DPU_ERROR("invalid encoder\n");
|
|
return;
|
|
}
|
|
|
|
DPU_DEBUG_VIDENC(phys_enc, "\n");
|
|
kfree(phys_enc);
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_get_hw_resources(
|
|
struct dpu_encoder_phys *phys_enc,
|
|
struct dpu_encoder_hw_resources *hw_res)
|
|
{
|
|
hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
|
|
}
|
|
|
|
static int _dpu_encoder_phys_vid_wait_for_vblank(
|
|
struct dpu_encoder_phys *phys_enc, bool notify)
|
|
{
|
|
struct dpu_encoder_wait_info wait_info;
|
|
int ret;
|
|
|
|
if (!phys_enc) {
|
|
pr_err("invalid encoder\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
wait_info.wq = &phys_enc->pending_kickoff_wq;
|
|
wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
|
|
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
|
|
|
|
if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
|
|
if (notify && phys_enc->parent_ops->handle_frame_done)
|
|
phys_enc->parent_ops->handle_frame_done(
|
|
phys_enc->parent, phys_enc,
|
|
DPU_ENCODER_FRAME_EVENT_DONE);
|
|
return 0;
|
|
}
|
|
|
|
/* Wait for kickoff to complete */
|
|
ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC,
|
|
&wait_info);
|
|
|
|
if (ret == -ETIMEDOUT) {
|
|
dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
|
|
} else if (!ret && notify && phys_enc->parent_ops->handle_frame_done)
|
|
phys_enc->parent_ops->handle_frame_done(
|
|
phys_enc->parent, phys_enc,
|
|
DPU_ENCODER_FRAME_EVENT_DONE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dpu_encoder_phys_vid_wait_for_vblank(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
return _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, true);
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_prepare_for_kickoff(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct dpu_hw_ctl *ctl;
|
|
int rc;
|
|
|
|
if (!phys_enc) {
|
|
DPU_ERROR("invalid encoder/parameters\n");
|
|
return;
|
|
}
|
|
|
|
ctl = phys_enc->hw_ctl;
|
|
if (!ctl || !ctl->ops.wait_reset_status)
|
|
return;
|
|
|
|
/*
|
|
* hw supports hardware initiated ctl reset, so before we kickoff a new
|
|
* frame, need to check and wait for hw initiated ctl reset completion
|
|
*/
|
|
rc = ctl->ops.wait_reset_status(ctl);
|
|
if (rc) {
|
|
DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
|
|
ctl->idx, rc);
|
|
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
|
|
}
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
struct msm_drm_private *priv;
|
|
unsigned long lock_flags;
|
|
int ret;
|
|
|
|
if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
|
|
!phys_enc->parent->dev->dev_private) {
|
|
DPU_ERROR("invalid encoder/device\n");
|
|
return;
|
|
}
|
|
priv = phys_enc->parent->dev->dev_private;
|
|
|
|
if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
|
|
DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
|
|
phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
|
|
return;
|
|
}
|
|
|
|
if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
|
|
return;
|
|
|
|
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
|
|
DPU_ERROR("already disabled\n");
|
|
return;
|
|
}
|
|
|
|
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
|
|
phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
|
|
if (dpu_encoder_phys_vid_is_master(phys_enc))
|
|
dpu_encoder_phys_inc_pending(phys_enc);
|
|
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
|
|
|
|
/*
|
|
* Wait for a vsync so we know the ENABLE=0 latched before
|
|
* the (connector) source of the vsync's gets disabled,
|
|
* otherwise we end up in a funny state if we re-enable
|
|
* before the disable latches, which results that some of
|
|
* the settings changes for the new modeset (like new
|
|
* scanout buffer) don't latch properly..
|
|
*/
|
|
if (dpu_encoder_phys_vid_is_master(phys_enc)) {
|
|
ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
|
|
if (ret) {
|
|
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
|
|
DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
|
|
DRMID(phys_enc->parent),
|
|
phys_enc->hw_intf->idx - INTF_0, ret);
|
|
}
|
|
}
|
|
|
|
phys_enc->enable_state = DPU_ENC_DISABLED;
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_handle_post_kickoff(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
unsigned long lock_flags;
|
|
|
|
if (!phys_enc) {
|
|
DPU_ERROR("invalid encoder\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Video mode must flush CTL before enabling timing engine
|
|
* Video encoders need to turn on their interfaces now
|
|
*/
|
|
if (phys_enc->enable_state == DPU_ENC_ENABLING) {
|
|
trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
|
|
phys_enc->hw_intf->idx - INTF_0);
|
|
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
|
|
phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
|
|
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
|
|
phys_enc->enable_state = DPU_ENC_ENABLED;
|
|
}
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
|
|
bool enable)
|
|
{
|
|
int ret;
|
|
|
|
if (!phys_enc)
|
|
return;
|
|
|
|
trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
|
|
phys_enc->hw_intf->idx - INTF_0,
|
|
enable,
|
|
atomic_read(&phys_enc->vblank_refcount));
|
|
|
|
if (enable) {
|
|
ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
|
|
if (ret)
|
|
return;
|
|
|
|
dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
|
|
} else {
|
|
dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
|
|
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
|
|
}
|
|
}
|
|
|
|
static int dpu_encoder_phys_vid_get_line_count(
|
|
struct dpu_encoder_phys *phys_enc)
|
|
{
|
|
if (!phys_enc)
|
|
return -EINVAL;
|
|
|
|
if (!dpu_encoder_phys_vid_is_master(phys_enc))
|
|
return -EINVAL;
|
|
|
|
if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
|
|
return -EINVAL;
|
|
|
|
return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
|
|
}
|
|
|
|
static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
|
|
{
|
|
ops->is_master = dpu_encoder_phys_vid_is_master;
|
|
ops->mode_set = dpu_encoder_phys_vid_mode_set;
|
|
ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup;
|
|
ops->enable = dpu_encoder_phys_vid_enable;
|
|
ops->disable = dpu_encoder_phys_vid_disable;
|
|
ops->destroy = dpu_encoder_phys_vid_destroy;
|
|
ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;
|
|
ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
|
|
ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_vblank;
|
|
ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
|
|
ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
|
|
ops->irq_control = dpu_encoder_phys_vid_irq_control;
|
|
ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
|
|
ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
|
|
ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
|
|
ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
|
|
}
|
|
|
|
struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
|
|
struct dpu_enc_phys_init_params *p)
|
|
{
|
|
struct dpu_encoder_phys *phys_enc = NULL;
|
|
struct dpu_encoder_irq *irq;
|
|
int i, ret = 0;
|
|
|
|
if (!p) {
|
|
ret = -EINVAL;
|
|
goto fail;
|
|
}
|
|
|
|
phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
|
|
if (!phys_enc) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
|
|
phys_enc->intf_idx = p->intf_idx;
|
|
|
|
DPU_DEBUG_VIDENC(phys_enc, "\n");
|
|
|
|
dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
|
|
phys_enc->parent = p->parent;
|
|
phys_enc->parent_ops = p->parent_ops;
|
|
phys_enc->dpu_kms = p->dpu_kms;
|
|
phys_enc->split_role = p->split_role;
|
|
phys_enc->intf_mode = INTF_MODE_VIDEO;
|
|
phys_enc->enc_spinlock = p->enc_spinlock;
|
|
for (i = 0; i < INTR_IDX_MAX; i++) {
|
|
irq = &phys_enc->irq[i];
|
|
INIT_LIST_HEAD(&irq->cb.list);
|
|
irq->irq_idx = -EINVAL;
|
|
irq->hw_idx = -EINVAL;
|
|
irq->cb.arg = phys_enc;
|
|
}
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_VSYNC];
|
|
irq->name = "vsync_irq";
|
|
irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
|
|
irq->intr_idx = INTR_IDX_VSYNC;
|
|
irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
|
|
|
|
irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
|
|
irq->name = "underrun";
|
|
irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
|
|
irq->intr_idx = INTR_IDX_UNDERRUN;
|
|
irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
|
|
|
|
atomic_set(&phys_enc->vblank_refcount, 0);
|
|
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
|
|
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
|
|
phys_enc->enable_state = DPU_ENC_DISABLED;
|
|
|
|
DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
|
|
|
|
return phys_enc;
|
|
|
|
fail:
|
|
DPU_ERROR("failed to create encoder\n");
|
|
if (phys_enc)
|
|
dpu_encoder_phys_vid_destroy(phys_enc);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|