66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2017 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_S32V234_H
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#define __DT_BINDINGS_CLOCK_S32V234_H
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#define S32V234_CLK_DUMMY 0
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#define S32V234_CLK_FXOSC 1
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#define S32V234_CLK_FIRC 2
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/* PERIPH PLL */
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#define S32V234_CLK_PERIPHPLL_SRC_SEL 3
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#define S32V234_CLK_PERIPHPLL_VCO 4
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#define S32V234_CLK_PERIPHPLL_PHI0 5
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#define S32V234_CLK_PERIPHPLL_PHI0_DIV3 6
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#define S32V234_CLK_PERIPHPLL_PHI0_DIV5 7
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#define S32V234_CLK_PERIPHPLL_PHI1 8
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/* LINFlexD Clock */
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#define S32V234_CLK_LIN 9
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#define S32V234_CLK_LIN_SEL 10
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#define S32V234_CLK_LIN_IPG 11
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/* SDHC Clock */
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#define S32V234_CLK_SDHC 12
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#define S32V234_CLK_SDHC_SEL 13
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/* ENET PLL */
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#define S32V234_CLK_ENETPLL_SRC_SEL 14
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#define S32V234_CLK_ENETPLL_VCO 15
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#define S32V234_CLK_ENETPLL_PHI0 16
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#define S32V234_CLK_ENETPLL_PHI1 17
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#define S32V234_CLK_ENETPLL_DFS0 18
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#define S32V234_CLK_ENETPLL_DFS1 19
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#define S32V234_CLK_ENETPLL_DFS2 20
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#define S32V234_CLK_ENETPLL_DFS3 21
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/* System Clock */
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#define S32V234_CLK_SYS_SEL 22
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#define S32V234_CLK_SYS3 23
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#define S32V234_CLK_SYS6 24
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#define S32V234_CLK_SYS6_DIV2 25
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/* ENET Clock */
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#define S32V234_CLK_ENET_TIME_DIV 26
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#define S32V234_CLK_ENET_TIME_SEL 27
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#define S32V234_CLK_ENET_DIV 28
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#define S32V234_CLK_ENET_SEL 29
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#define S32V234_CLK_ENET 30
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#define S32V234_CLK_ENET_TIME 31
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/* ARM PLL */
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#define S32V234_CLK_ARMPLL_SRC_SEL 32
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#define S32V234_CLK_ARMPLL_VCO 33
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#define S32V234_CLK_ARMPLL_PHI0 34
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#define S32V234_CLK_ARMPLL_PHI1 35
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#define S32V234_CLK_ARMPLL_DFS0 35
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#define S32V234_CLK_ARMPLL_DFS1 36
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#define S32V234_CLK_ARMPLL_DFS2 37
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/* CAN Clock */
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#define S32V234_CLK_CAN 38
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#define S32V234_CLK_CAN_SEL 39
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#define S32V234_CLK_END 40
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#endif /* __DT_BINDINGS_CLOCK_S32V234_H */
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