300459d558
IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS,
IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of
IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1
to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to
bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver
more information about IPIs.
Why we change code in arch/mips/loongson/common/setup.c?
If without this change, when SMP configured, system cannot boot since
it hang at printk() in cgroup_init_early(). The root cause is:
console_trylock()
\-->down_trylock(&console_sem)
\-->raw_spin_unlock_irqrestore(&sem->lock, flags)
\-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions)
\-->__raw_spin_unlock_irqrestore() (following is the SMP case)
\-->do_raw_spin_unlock()
\-->arch_spin_unlock()
\-->nudge_writes()
\-->mb()
\-->wbflush()
\-->__wbflush()
In previous code __wbflush() is initialized in plat_mem_setup(), but
cgroup_init_early() is called before plat_mem_setup(). Therefore, In
this patch we make changes to avoid boot failure.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6638
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
30 lines
753 B
C
30 lines
753 B
C
#ifndef __LOONGSON_SMP_H_
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#define __LOONGSON_SMP_H_
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/* for Loongson-3A smp support */
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/* 4 groups(nodes) in maximum in numa case */
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#define SMP_CORE_GROUP0_BASE 0x900000003ff01000
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#define SMP_CORE_GROUP1_BASE 0x900010003ff01000
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#define SMP_CORE_GROUP2_BASE 0x900020003ff01000
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#define SMP_CORE_GROUP3_BASE 0x900030003ff01000
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/* 4 cores in each group(node) */
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#define SMP_CORE0_OFFSET 0x000
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#define SMP_CORE1_OFFSET 0x100
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#define SMP_CORE2_OFFSET 0x200
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#define SMP_CORE3_OFFSET 0x300
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/* ipi registers offsets */
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#define STATUS0 0x00
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#define EN0 0x04
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#define SET0 0x08
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#define CLEAR0 0x0c
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#define STATUS1 0x10
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#define MASK1 0x14
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#define SET1 0x18
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#define CLEAR1 0x1c
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#define BUF 0x20
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#endif
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