David Daney 9e290a19f2 MIPS: Remove execution hazard barriers for Octeon. ... The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2009-06-17 11:06:26 +01:00
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cpu-feature-overrides.h	MIPS: Remove execution hazard barriers for Octeon.	2009-06-17 11:06:26 +01:00
dma-coherence.h	MIPS: Pass struct device to plat_dma_addr_to_phys()	2009-06-17 11:06:24 +01:00
irq.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00
kernel-entry-init.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00
war.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00