2005-04-16 16:20:36 -06:00
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/*
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2014-01-01 08:35:32 -07:00
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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2005-04-16 16:20:36 -06:00
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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2013-10-30 14:52:10 -06:00
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* Copyright (C) 2013 Imagination Technologies Ltd.
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2005-04-16 16:20:36 -06:00
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*
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* Routines for generic manipulation of the interrupts found on the MIPS
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2014-01-01 08:35:32 -07:00
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* Malta board. The interrupt controller is located in the South Bridge
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* a PIIX4 device with two internal 82C95 interrupt controllers.
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2005-04-16 16:20:36 -06:00
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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2009-06-19 07:05:26 -06:00
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#include <linux/smp.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/interrupt.h>
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2008-01-24 09:52:49 -07:00
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#include <linux/io.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/kernel_stat.h>
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2007-02-04 19:42:11 -07:00
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#include <linux/kernel.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/random.h>
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2008-04-28 10:14:26 -06:00
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#include <asm/traps.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/i8259.h>
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2005-07-14 09:57:16 -06:00
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#include <asm/irq_cpu.h>
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2006-10-15 02:17:43 -06:00
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#include <asm/irq_regs.h>
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2014-01-15 03:31:54 -07:00
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#include <asm/mips-cm.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/gt64120.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/msc01_pci.h>
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2005-07-14 09:57:16 -06:00
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#include <asm/msc01_ic.h>
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2008-04-28 10:14:26 -06:00
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#include <asm/gic.h>
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2012-03-28 11:30:02 -06:00
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#include <asm/setup.h>
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2013-10-30 14:52:10 -06:00
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#include <asm/rtlx.h>
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2008-04-28 10:14:26 -06:00
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2014-10-20 13:03:51 -06:00
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static void __iomem *_msc01_biu_base;
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2005-04-16 16:20:36 -06:00
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2010-02-27 04:53:32 -07:00
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static DEFINE_RAW_SPINLOCK(mips_irq_lock);
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2005-04-16 16:20:36 -06:00
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static inline int mips_pcibios_iack(void)
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{
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int irq;
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/*
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* Determine highest priority pending interrupt by performing
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* a PCI Interrupt Acknowledge cycle.
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*/
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2007-04-27 08:58:41 -06:00
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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2008-01-24 09:52:45 -07:00
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MSC_READ(MSC01_PCI_IACK, irq);
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2005-04-16 16:20:36 -06:00
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irq &= 0xff;
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break;
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2007-04-27 08:58:41 -06:00
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case MIPS_REVISION_SCON_GT64120:
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2005-04-16 16:20:36 -06:00
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irq = GT_READ(GT_PCI0_IACK_OFS);
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irq &= 0xff;
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break;
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2007-04-27 08:58:41 -06:00
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case MIPS_REVISION_SCON_BONITO:
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2005-04-16 16:20:36 -06:00
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/* The following will generate a PCI IACK cycle on the
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* Bonito controller. It's a little bit kludgy, but it
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* was the easiest way to implement it in hardware at
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* the given time.
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*/
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BONITO_PCIMAP_CFG = 0x20000;
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/* Flush Bonito register block */
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2011-03-29 03:48:22 -06:00
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(void) BONITO_PCIMAP_CFG;
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2013-01-22 04:59:30 -07:00
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iob(); /* sync */
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2005-04-16 16:20:36 -06:00
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2009-07-10 02:53:54 -06:00
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irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
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2013-01-22 04:59:30 -07:00
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iob(); /* sync */
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2005-04-16 16:20:36 -06:00
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irq &= 0xff;
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BONITO_PCIMAP_CFG = 0;
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break;
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default:
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2014-01-01 08:35:32 -07:00
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pr_emerg("Unknown system controller.\n");
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2005-04-16 16:20:36 -06:00
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return -1;
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}
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return irq;
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}
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2005-07-14 09:57:16 -06:00
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static inline int get_int(void)
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2005-04-16 16:20:36 -06:00
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{
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unsigned long flags;
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2005-07-14 09:57:16 -06:00
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int irq;
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2010-02-27 04:53:32 -07:00
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raw_spin_lock_irqsave(&mips_irq_lock, flags);
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2005-04-16 16:20:36 -06:00
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2005-07-14 09:57:16 -06:00
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irq = mips_pcibios_iack();
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2005-04-16 16:20:36 -06:00
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/*
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2005-08-16 09:44:06 -06:00
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* The only way we can decide if an interrupt is spurious
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* is by checking the 8259 registers. This needs a spinlock
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* on an SMP system, so leave it up to the generic code...
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2005-04-16 16:20:36 -06:00
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*/
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2010-02-27 04:53:32 -07:00
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raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
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2005-04-16 16:20:36 -06:00
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2005-07-14 09:57:16 -06:00
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return irq;
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2005-04-16 16:20:36 -06:00
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}
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2006-10-07 12:44:33 -06:00
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static void malta_hw0_irqdispatch(void)
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2005-04-16 16:20:36 -06:00
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{
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int irq;
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2005-07-14 09:57:16 -06:00
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irq = get_int();
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2006-04-05 02:45:45 -06:00
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if (irq < 0) {
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2008-01-24 09:52:54 -07:00
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/* interrupt has already been cleared */
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return;
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2006-04-05 02:45:45 -06:00
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}
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2005-04-16 16:20:36 -06:00
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2006-10-07 12:44:33 -06:00
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do_IRQ(MALTA_INT_BASE + irq);
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2013-10-30 14:52:10 -06:00
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2014-02-28 11:23:01 -07:00
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#ifdef CONFIG_MIPS_VPE_APSP_API_MT
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2013-10-30 14:52:10 -06:00
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if (aprp_hook)
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aprp_hook();
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#endif
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2005-04-16 16:20:36 -06:00
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}
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2014-09-18 15:47:24 -06:00
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static irqreturn_t i8259_handler(int irq, void *dev_id)
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2008-04-28 10:14:26 -06:00
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{
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2014-09-18 15:47:24 -06:00
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malta_hw0_irqdispatch();
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return IRQ_HANDLED;
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2008-04-28 10:14:26 -06:00
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}
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2006-10-07 12:44:33 -06:00
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static void corehi_irqdispatch(void)
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2005-04-16 16:20:36 -06:00
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{
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2006-10-07 12:44:33 -06:00
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unsigned int intedge, intsteer, pcicmd, pcibadaddr;
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2008-01-24 09:52:45 -07:00
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unsigned int pcimstat, intisr, inten, intpol;
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2007-10-11 16:46:15 -06:00
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unsigned int intrcause, datalo, datahi;
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2006-10-15 02:17:43 -06:00
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struct pt_regs *regs = get_irq_regs();
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2005-04-16 16:20:36 -06:00
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2014-01-01 08:35:32 -07:00
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pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
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pr_emerg("epc : %08lx\nStatus: %08lx\n"
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"Cause : %08lx\nbadVaddr : %08lx\n",
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regs->cp0_epc, regs->cp0_status,
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regs->cp0_cause, regs->cp0_badvaddr);
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2005-07-14 09:57:16 -06:00
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/* Read all the registers and then print them as there is a
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problem with interspersed printk's upsetting the Bonito controller.
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Do it for the others too.
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*/
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2007-04-27 08:58:41 -06:00
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switch (mips_revision_sconid) {
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2008-01-24 09:52:45 -07:00
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case MIPS_REVISION_SCON_SOCIT:
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2007-04-27 08:58:41 -06:00
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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2008-01-24 09:52:45 -07:00
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ll_msc_irq();
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break;
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case MIPS_REVISION_SCON_GT64120:
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intrcause = GT_READ(GT_INTRCAUSE_OFS);
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datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
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datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
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2014-01-01 08:35:32 -07:00
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pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
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pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
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2008-01-24 09:52:42 -07:00
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datahi, datalo);
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2008-01-24 09:52:45 -07:00
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break;
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case MIPS_REVISION_SCON_BONITO:
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pcibadaddr = BONITO_PCIBADADDR;
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pcimstat = BONITO_PCIMSTAT;
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intisr = BONITO_INTISR;
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inten = BONITO_INTEN;
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intpol = BONITO_INTPOL;
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intedge = BONITO_INTEDGE;
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intsteer = BONITO_INTSTEER;
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pcicmd = BONITO_PCICMD;
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2014-01-01 08:35:32 -07:00
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pr_emerg("BONITO_INTISR = %08x\n", intisr);
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pr_emerg("BONITO_INTEN = %08x\n", inten);
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pr_emerg("BONITO_INTPOL = %08x\n", intpol);
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pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
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pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
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pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
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pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
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pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
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2008-01-24 09:52:45 -07:00
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break;
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}
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2005-04-16 16:20:36 -06:00
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2008-01-24 09:52:45 -07:00
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die("CoreHi interrupt", regs);
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2005-04-16 16:20:36 -06:00
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}
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2014-09-18 15:47:24 -06:00
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static irqreturn_t corehi_handler(int irq, void *dev_id)
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{
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corehi_irqdispatch();
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return IRQ_HANDLED;
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}
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2008-04-28 10:14:26 -06:00
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#ifdef CONFIG_MIPS_MT_SMP
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#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
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#define C_RESCHED C_SW0
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#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
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#define C_CALL C_SW1
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static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
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static void ipi_resched_dispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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}
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static void ipi_call_dispatch(void)
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{
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do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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2014-02-28 11:23:01 -07:00
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#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
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2013-10-30 14:52:10 -06:00
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if (aprp_hook)
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aprp_hook();
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#endif
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2011-04-05 09:23:39 -06:00
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scheduler_ipi();
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2008-04-28 10:14:26 -06:00
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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2011-11-22 07:38:03 -07:00
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.flags = IRQF_PERCPU,
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2008-04-28 10:14:26 -06:00
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.name = "IPI_resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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2011-11-22 07:38:03 -07:00
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.flags = IRQF_PERCPU,
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2008-04-28 10:14:26 -06:00
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.name = "IPI_call"
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};
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2014-09-18 15:47:24 -06:00
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#endif /* CONFIG_MIPS_MT_SMP */
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2008-04-28 10:14:26 -06:00
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2005-07-14 09:57:16 -06:00
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static struct irqaction i8259irq = {
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2014-09-18 15:47:24 -06:00
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.handler = i8259_handler,
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2011-07-23 06:41:24 -06:00
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.name = "XT-PIC cascade",
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.flags = IRQF_NO_THREAD,
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2005-07-14 09:57:16 -06:00
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};
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static struct irqaction corehi_irqaction = {
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2014-09-18 15:47:24 -06:00
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.handler = corehi_handler,
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2011-07-23 06:41:24 -06:00
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.name = "CoreHi",
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.flags = IRQF_NO_THREAD,
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2005-07-14 09:57:16 -06:00
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};
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2014-01-01 08:35:32 -07:00
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static msc_irqmap_t msc_irqmap[] __initdata = {
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2005-07-14 09:57:16 -06:00
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{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
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};
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2014-01-01 08:35:32 -07:00
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static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
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2005-07-14 09:57:16 -06:00
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2014-01-01 08:35:32 -07:00
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static msc_irqmap_t msc_eicirqmap[] __initdata = {
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2005-07-14 09:57:16 -06:00
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{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
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};
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2008-04-28 10:14:26 -06:00
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|
2014-01-01 08:35:32 -07:00
|
|
|
static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
|
2005-07-14 09:57:16 -06:00
|
|
|
|
2009-07-10 02:54:09 -06:00
|
|
|
void __init arch_init_ipiirq(int irq, struct irqaction *action)
|
|
|
|
{
|
|
|
|
setup_irq(irq, action);
|
2011-03-27 07:19:28 -06:00
|
|
|
irq_set_handler(irq, handle_percpu_irq);
|
2009-07-10 02:54:09 -06:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
void __init arch_init_irq(void)
|
|
|
|
{
|
2014-09-18 15:47:24 -06:00
|
|
|
int corehi_irq, i8259_irq;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
init_i8259_irqs();
|
2005-07-14 09:57:16 -06:00
|
|
|
|
|
|
|
if (!cpu_has_veic)
|
2007-01-07 10:14:29 -07:00
|
|
|
mips_cpu_irq_init();
|
2005-07-14 09:57:16 -06:00
|
|
|
|
2014-01-15 03:31:54 -07:00
|
|
|
if (mips_cm_present()) {
|
|
|
|
write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
|
2008-04-28 10:14:26 -06:00
|
|
|
gic_present = 1;
|
|
|
|
} else {
|
2009-07-10 02:54:25 -06:00
|
|
|
if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
|
2014-10-20 13:03:51 -06:00
|
|
|
_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
|
2009-07-10 02:54:25 -06:00
|
|
|
MSC01_BIU_ADDRSPACE_SZ);
|
2014-10-20 13:03:51 -06:00
|
|
|
gic_present =
|
|
|
|
(__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
|
|
|
|
MSC01_SC_CFG_GICPRES_MSK) >>
|
|
|
|
MSC01_SC_CFG_GICPRES_SHF;
|
2009-07-10 02:54:25 -06:00
|
|
|
}
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
|
|
|
if (gic_present)
|
2009-07-10 02:54:09 -06:00
|
|
|
pr_debug("GIC present\n");
|
2008-04-28 10:14:26 -06:00
|
|
|
|
2008-01-24 09:52:45 -07:00
|
|
|
switch (mips_revision_sconid) {
|
|
|
|
case MIPS_REVISION_SCON_SOCIT:
|
|
|
|
case MIPS_REVISION_SCON_ROCIT:
|
2007-05-08 07:05:39 -06:00
|
|
|
if (cpu_has_veic)
|
2008-01-24 09:52:47 -07:00
|
|
|
init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
|
|
|
|
MSC01E_INT_BASE, msc_eicirqmap,
|
|
|
|
msc_nr_eicirqs);
|
2007-05-08 07:05:39 -06:00
|
|
|
else
|
2008-01-24 09:52:47 -07:00
|
|
|
init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
|
|
|
|
MSC01C_INT_BASE, msc_irqmap,
|
|
|
|
msc_nr_irqs);
|
2007-05-08 07:05:39 -06:00
|
|
|
break;
|
|
|
|
|
2008-01-24 09:52:45 -07:00
|
|
|
case MIPS_REVISION_SCON_SOCITSC:
|
|
|
|
case MIPS_REVISION_SCON_SOCITSCP:
|
2005-07-14 09:57:16 -06:00
|
|
|
if (cpu_has_veic)
|
2008-01-24 09:52:47 -07:00
|
|
|
init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
|
|
|
|
MSC01E_INT_BASE, msc_eicirqmap,
|
|
|
|
msc_nr_eicirqs);
|
2005-07-14 09:57:16 -06:00
|
|
|
else
|
2008-01-24 09:52:47 -07:00
|
|
|
init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
|
|
|
|
MSC01C_INT_BASE, msc_irqmap,
|
|
|
|
msc_nr_irqs);
|
2005-07-14 09:57:16 -06:00
|
|
|
}
|
|
|
|
|
2008-04-28 10:14:26 -06:00
|
|
|
if (gic_present) {
|
|
|
|
int i;
|
2014-09-18 15:47:24 -06:00
|
|
|
|
|
|
|
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
|
|
|
|
MIPS_GIC_IRQ_BASE);
|
2014-01-15 03:31:54 -07:00
|
|
|
if (!mips_cm_present()) {
|
2008-04-28 10:14:26 -06:00
|
|
|
/* Enable the GIC */
|
2014-10-20 13:03:51 -06:00
|
|
|
i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
|
|
|
|
__raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
|
|
|
|
_msc01_biu_base + MSC01_SC_CFG_OFS);
|
2008-04-28 10:14:26 -06:00
|
|
|
pr_debug("GIC Enabled\n");
|
|
|
|
}
|
2014-09-18 15:47:24 -06:00
|
|
|
i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
|
|
|
|
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
|
2008-04-28 10:14:26 -06:00
|
|
|
} else {
|
2009-07-10 02:54:09 -06:00
|
|
|
#if defined(CONFIG_MIPS_MT_SMP)
|
2008-04-28 10:14:26 -06:00
|
|
|
/* set up ipi interrupts */
|
|
|
|
if (cpu_has_veic) {
|
|
|
|
set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
|
|
|
|
set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
|
|
|
|
cpu_ipi_resched_irq = MSC01E_INT_SW0;
|
|
|
|
cpu_ipi_call_irq = MSC01E_INT_SW1;
|
|
|
|
} else {
|
2014-01-01 08:35:32 -07:00
|
|
|
cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
|
|
|
|
MIPS_CPU_IPI_RESCHED_IRQ;
|
|
|
|
cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
|
|
|
|
MIPS_CPU_IPI_CALL_IRQ;
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
2009-07-10 02:54:09 -06:00
|
|
|
arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
|
|
|
|
arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
|
2008-04-28 10:14:26 -06:00
|
|
|
#endif
|
2014-09-18 15:47:24 -06:00
|
|
|
if (cpu_has_veic) {
|
|
|
|
set_vi_handler(MSC01E_INT_I8259A,
|
|
|
|
malta_hw0_irqdispatch);
|
|
|
|
set_vi_handler(MSC01E_INT_COREHI,
|
|
|
|
corehi_irqdispatch);
|
|
|
|
i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
|
|
|
|
corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
|
|
|
|
} else {
|
|
|
|
i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
|
|
|
|
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
|
|
|
|
}
|
2009-07-10 02:54:09 -06:00
|
|
|
}
|
2014-09-18 15:47:24 -06:00
|
|
|
|
|
|
|
setup_irq(i8259_irq, &i8259irq);
|
|
|
|
setup_irq(corehi_irq, &corehi_irqaction);
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void malta_be_init(void)
|
|
|
|
{
|
2014-01-01 08:35:32 -07:00
|
|
|
/* Could change CM error mask register. */
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static char *tr[8] = {
|
|
|
|
"mem", "gcr", "gic", "mmio",
|
2013-01-22 04:59:30 -07:00
|
|
|
"0x04", "0x05", "0x06", "0x07"
|
2008-04-28 10:14:26 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static char *mcmd[32] = {
|
|
|
|
[0x00] = "0x00",
|
|
|
|
[0x01] = "Legacy Write",
|
|
|
|
[0x02] = "Legacy Read",
|
|
|
|
[0x03] = "0x03",
|
|
|
|
[0x04] = "0x04",
|
|
|
|
[0x05] = "0x05",
|
|
|
|
[0x06] = "0x06",
|
|
|
|
[0x07] = "0x07",
|
|
|
|
[0x08] = "Coherent Read Own",
|
|
|
|
[0x09] = "Coherent Read Share",
|
|
|
|
[0x0a] = "Coherent Read Discard",
|
|
|
|
[0x0b] = "Coherent Ready Share Always",
|
|
|
|
[0x0c] = "Coherent Upgrade",
|
|
|
|
[0x0d] = "Coherent Writeback",
|
|
|
|
[0x0e] = "0x0e",
|
|
|
|
[0x0f] = "0x0f",
|
|
|
|
[0x10] = "Coherent Copyback",
|
|
|
|
[0x11] = "Coherent Copyback Invalidate",
|
|
|
|
[0x12] = "Coherent Invalidate",
|
|
|
|
[0x13] = "Coherent Write Invalidate",
|
|
|
|
[0x14] = "Coherent Completion Sync",
|
|
|
|
[0x15] = "0x15",
|
|
|
|
[0x16] = "0x16",
|
|
|
|
[0x17] = "0x17",
|
|
|
|
[0x18] = "0x18",
|
|
|
|
[0x19] = "0x19",
|
|
|
|
[0x1a] = "0x1a",
|
|
|
|
[0x1b] = "0x1b",
|
|
|
|
[0x1c] = "0x1c",
|
|
|
|
[0x1d] = "0x1d",
|
|
|
|
[0x1e] = "0x1e",
|
|
|
|
[0x1f] = "0x1f"
|
|
|
|
};
|
|
|
|
|
|
|
|
static char *core[8] = {
|
2013-01-22 04:59:30 -07:00
|
|
|
"Invalid/OK", "Invalid/Data",
|
2008-04-28 10:14:26 -06:00
|
|
|
"Shared/OK", "Shared/Data",
|
|
|
|
"Modified/OK", "Modified/Data",
|
2013-01-22 04:59:30 -07:00
|
|
|
"Exclusive/OK", "Exclusive/Data"
|
2008-04-28 10:14:26 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static char *causes[32] = {
|
|
|
|
"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
|
|
|
|
"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
|
|
|
|
"0x08", "0x09", "0x0a", "0x0b",
|
|
|
|
"0x0c", "0x0d", "0x0e", "0x0f",
|
|
|
|
"0x10", "0x11", "0x12", "0x13",
|
|
|
|
"0x14", "0x15", "0x16", "INTVN_WR_ERR",
|
|
|
|
"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
|
|
|
|
"0x1c", "0x1d", "0x1e", "0x1f"
|
|
|
|
};
|
|
|
|
|
|
|
|
int malta_be_handler(struct pt_regs *regs, int is_fixup)
|
|
|
|
{
|
|
|
|
/* This duplicates the handling in do_be which seems wrong */
|
|
|
|
int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
|
|
|
|
|
2014-01-15 03:31:54 -07:00
|
|
|
if (mips_cm_present()) {
|
|
|
|
unsigned long cm_error = read_gcr_error_cause();
|
|
|
|
unsigned long cm_addr = read_gcr_error_addr();
|
|
|
|
unsigned long cm_other = read_gcr_error_mult();
|
2008-04-28 10:14:26 -06:00
|
|
|
unsigned long cause, ocause;
|
|
|
|
char buf[256];
|
|
|
|
|
2014-01-15 03:31:54 -07:00
|
|
|
cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
|
2008-04-28 10:14:26 -06:00
|
|
|
if (cause != 0) {
|
2014-01-15 03:31:54 -07:00
|
|
|
cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
|
2008-04-28 10:14:26 -06:00
|
|
|
if (cause < 16) {
|
|
|
|
unsigned long cca_bits = (cm_error >> 15) & 7;
|
|
|
|
unsigned long tr_bits = (cm_error >> 12) & 7;
|
2014-01-01 08:35:32 -07:00
|
|
|
unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
|
2008-04-28 10:14:26 -06:00
|
|
|
unsigned long stag_bits = (cm_error >> 3) & 15;
|
|
|
|
unsigned long sport_bits = (cm_error >> 0) & 7;
|
|
|
|
|
|
|
|
snprintf(buf, sizeof(buf),
|
|
|
|
"CCA=%lu TR=%s MCmd=%s STag=%lu "
|
|
|
|
"SPort=%lu\n",
|
2014-01-01 08:35:32 -07:00
|
|
|
cca_bits, tr[tr_bits], mcmd[cmd_bits],
|
2008-04-28 10:14:26 -06:00
|
|
|
stag_bits, sport_bits);
|
|
|
|
} else {
|
|
|
|
/* glob state & sresp together */
|
|
|
|
unsigned long c3_bits = (cm_error >> 18) & 7;
|
|
|
|
unsigned long c2_bits = (cm_error >> 15) & 7;
|
|
|
|
unsigned long c1_bits = (cm_error >> 12) & 7;
|
|
|
|
unsigned long c0_bits = (cm_error >> 9) & 7;
|
|
|
|
unsigned long sc_bit = (cm_error >> 8) & 1;
|
2014-01-01 08:35:32 -07:00
|
|
|
unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
|
2008-04-28 10:14:26 -06:00
|
|
|
unsigned long sport_bits = (cm_error >> 0) & 7;
|
|
|
|
snprintf(buf, sizeof(buf),
|
|
|
|
"C3=%s C2=%s C1=%s C0=%s SC=%s "
|
|
|
|
"MCmd=%s SPort=%lu\n",
|
|
|
|
core[c3_bits], core[c2_bits],
|
|
|
|
core[c1_bits], core[c0_bits],
|
|
|
|
sc_bit ? "True" : "False",
|
2014-01-01 08:35:32 -07:00
|
|
|
mcmd[cmd_bits], sport_bits);
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
|
|
|
|
2014-01-15 03:31:54 -07:00
|
|
|
ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
|
|
|
|
CM_GCR_ERROR_MULT_ERR2ND_SHF;
|
2008-04-28 10:14:26 -06:00
|
|
|
|
2014-01-01 08:35:32 -07:00
|
|
|
pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
|
2008-04-28 10:14:26 -06:00
|
|
|
causes[cause], buf);
|
2014-01-01 08:35:32 -07:00
|
|
|
pr_err("CM_ADDR =%08lx\n", cm_addr);
|
|
|
|
pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
|
2008-04-28 10:14:26 -06:00
|
|
|
|
|
|
|
/* reprime cause register */
|
2014-01-15 03:31:54 -07:00
|
|
|
write_gcr_error_cause(0);
|
2008-04-28 10:14:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|