2012-03-16 00:11:20 -06:00
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/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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2013-01-15 03:28:05 -07:00
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#include <linux/log2.h>
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2012-03-16 00:11:20 -06:00
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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2015-04-13 17:03:21 -06:00
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* rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
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2012-03-16 00:11:20 -06:00
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* parent - fixed parent. No clk_set_parent support
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*/
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2015-01-19 19:05:29 -07:00
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#define div_mask(width) ((1 << (width)) - 1)
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2012-05-17 04:22:13 -06:00
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2015-11-30 18:31:38 -07:00
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
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u8 width)
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2012-06-29 07:36:32 -06:00
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{
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2015-11-30 18:31:38 -07:00
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unsigned int maxdiv = 0, mask = div_mask(width);
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2012-06-29 07:36:32 -06:00
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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2015-11-30 18:31:38 -07:00
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if (clkt->div > maxdiv && clkt->val <= mask)
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2012-06-29 07:36:32 -06:00
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maxdiv = clkt->div;
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return maxdiv;
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}
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2014-01-29 09:24:07 -07:00
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static unsigned int _get_table_mindiv(const struct clk_div_table *table)
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{
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unsigned int mindiv = UINT_MAX;
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div < mindiv)
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mindiv = clkt->div;
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return mindiv;
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}
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2015-01-19 19:05:29 -07:00
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static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
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unsigned long flags)
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2012-05-17 04:22:13 -06:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_ONE_BASED)
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return div_mask(width);
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << div_mask(width);
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if (table)
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2015-11-30 18:31:38 -07:00
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return _get_table_maxdiv(table, width);
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2015-01-19 19:05:29 -07:00
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return div_mask(width) + 1;
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2012-05-17 04:22:13 -06:00
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}
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2012-06-29 07:36:32 -06:00
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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2015-01-19 19:05:29 -07:00
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static unsigned int _get_div(const struct clk_div_table *table,
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2015-05-15 13:45:47 -06:00
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unsigned int val, unsigned long flags, u8 width)
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2012-05-17 04:22:13 -06:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_ONE_BASED)
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2012-05-17 04:22:13 -06:00
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return val;
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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2012-05-17 04:22:13 -06:00
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return 1 << val;
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2015-05-15 13:45:47 -06:00
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if (flags & CLK_DIVIDER_MAX_AT_ZERO)
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return val ? val : div_mask(width) + 1;
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2015-01-19 19:05:29 -07:00
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if (table)
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return _get_table_div(table, val);
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2012-05-17 04:22:13 -06:00
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return val + 1;
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}
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2012-06-29 07:36:32 -06:00
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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2015-01-19 19:05:29 -07:00
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static unsigned int _get_val(const struct clk_div_table *table,
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2015-05-15 13:45:47 -06:00
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unsigned int div, unsigned long flags, u8 width)
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2012-05-17 04:22:13 -06:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_ONE_BASED)
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2012-05-17 04:22:13 -06:00
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return div;
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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2012-05-17 04:22:13 -06:00
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return __ffs(div);
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2015-05-15 13:45:47 -06:00
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if (flags & CLK_DIVIDER_MAX_AT_ZERO)
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return (div == div_mask(width) + 1) ? 0 : div;
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2015-01-19 19:05:29 -07:00
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if (table)
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return _get_table_val(table, div);
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2012-05-17 04:22:13 -06:00
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return div - 1;
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}
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2012-03-16 00:11:20 -06:00
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2015-01-19 19:05:29 -07:00
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unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
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unsigned int val,
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const struct clk_div_table *table,
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unsigned long flags)
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2012-03-16 00:11:20 -06:00
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{
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2015-05-15 13:45:47 -06:00
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struct clk_divider *divider = to_clk_divider(hw);
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2015-01-19 19:05:29 -07:00
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unsigned int div;
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2012-03-16 00:11:20 -06:00
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2015-05-15 13:45:47 -06:00
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div = _get_div(table, val, flags, divider->width);
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2012-05-17 04:22:13 -06:00
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if (!div) {
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2015-01-19 19:05:29 -07:00
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WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
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2013-04-02 16:36:56 -06:00
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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2015-07-30 18:20:57 -06:00
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clk_hw_get_name(hw));
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2012-05-17 04:22:13 -06:00
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return parent_rate;
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}
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2012-03-16 00:11:20 -06:00
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2015-04-13 17:03:21 -06:00
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return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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2012-03-16 00:11:20 -06:00
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}
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2015-01-19 19:05:29 -07:00
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EXPORT_SYMBOL_GPL(divider_recalc_rate);
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int val;
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val = clk_readl(divider->reg) >> divider->shift;
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val &= div_mask(divider->width);
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return divider_recalc_rate(hw, parent_rate, val, divider->table,
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divider->flags);
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}
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2012-03-16 00:11:20 -06:00
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2012-06-29 07:36:32 -06:00
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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2015-01-19 19:05:29 -07:00
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static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
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unsigned long flags)
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2012-06-29 07:36:32 -06:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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2013-01-15 03:28:05 -07:00
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return is_power_of_2(div);
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2015-01-19 19:05:29 -07:00
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if (table)
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return _is_valid_table_div(table, div);
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2012-06-29 07:36:32 -06:00
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return true;
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}
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2014-01-29 09:24:06 -07:00
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static int _round_up_table(const struct clk_div_table *table, int div)
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{
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const struct clk_div_table *clkt;
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2014-05-07 10:48:52 -06:00
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int up = INT_MAX;
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2014-01-29 09:24:06 -07:00
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div < div)
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continue;
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if ((clkt->div - div) < (up - div))
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up = clkt->div;
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}
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return up;
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}
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2014-01-29 09:24:07 -07:00
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static int _round_down_table(const struct clk_div_table *table, int div)
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{
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const struct clk_div_table *clkt;
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int down = _get_table_mindiv(table);
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div > div)
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continue;
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if ((div - clkt->div) < (div - down))
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down = clkt->div;
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}
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return down;
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}
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2015-01-19 19:05:29 -07:00
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static int _div_round_up(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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2014-01-29 09:24:06 -07:00
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{
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2015-04-13 17:03:21 -06:00
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int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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2014-01-29 09:24:06 -07:00
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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2014-01-29 09:24:06 -07:00
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div = __roundup_pow_of_two(div);
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2015-01-19 19:05:29 -07:00
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if (table)
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div = _round_up_table(table, div);
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2014-01-29 09:24:06 -07:00
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return div;
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}
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2015-01-19 19:05:29 -07:00
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static int _div_round_closest(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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2014-01-29 09:24:07 -07:00
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{
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2015-02-21 03:40:25 -07:00
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int up, down;
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2015-02-21 03:40:24 -07:00
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unsigned long up_rate, down_rate;
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2014-01-29 09:24:07 -07:00
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2015-04-13 17:03:21 -06:00
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up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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2015-02-21 03:40:25 -07:00
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down = parent_rate / rate;
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2014-01-29 09:24:07 -07:00
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO) {
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2015-02-21 03:40:25 -07:00
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up = __roundup_pow_of_two(up);
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down = __rounddown_pow_of_two(down);
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2015-01-19 19:05:29 -07:00
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} else if (table) {
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2015-02-21 03:40:25 -07:00
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up = _round_up_table(table, up);
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down = _round_down_table(table, down);
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2014-01-29 09:24:07 -07:00
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}
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2015-04-13 17:03:21 -06:00
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up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
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down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
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2015-02-21 03:40:24 -07:00
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return (rate - up_rate) <= (down_rate - rate) ? up : down;
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2014-01-29 09:24:07 -07:00
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}
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2015-01-19 19:05:29 -07:00
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static int _div_round(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate,
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unsigned long flags)
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2014-01-29 09:24:07 -07:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_ROUND_CLOSEST)
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return _div_round_closest(table, parent_rate, rate, flags);
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2014-01-29 09:24:07 -07:00
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2015-01-19 19:05:29 -07:00
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return _div_round_up(table, parent_rate, rate, flags);
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2014-01-29 09:24:07 -07:00
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}
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2015-01-19 19:05:29 -07:00
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static bool _is_best_div(unsigned long rate, unsigned long now,
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unsigned long best, unsigned long flags)
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2014-01-29 09:24:07 -07:00
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{
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_ROUND_CLOSEST)
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2014-01-29 09:24:07 -07:00
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return abs(rate - now) < abs(rate - best);
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return now <= rate && now > best;
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}
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2015-01-19 19:05:29 -07:00
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static int _next_div(const struct clk_div_table *table, int div,
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unsigned long flags)
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2014-01-29 09:24:08 -07:00
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{
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div++;
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2015-01-19 19:05:29 -07:00
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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2014-01-29 09:24:08 -07:00
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return __roundup_pow_of_two(div);
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2015-01-19 19:05:29 -07:00
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if (table)
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return _round_up_table(table, div);
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2014-01-29 09:24:08 -07:00
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return div;
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}
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2012-03-16 00:11:20 -06:00
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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2015-01-19 19:05:29 -07:00
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unsigned long *best_parent_rate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags)
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2012-03-16 00:11:20 -06:00
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{
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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2013-06-02 08:20:55 -06:00
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unsigned long parent_rate_saved = *best_parent_rate;
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2012-03-16 00:11:20 -06:00
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if (!rate)
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rate = 1;
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2015-01-19 19:05:29 -07:00
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maxdiv = _get_maxdiv(table, width, flags);
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2012-03-16 00:11:20 -06:00
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2015-06-29 17:56:30 -06:00
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|
|
if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
|
2012-04-12 06:50:17 -06:00
|
|
|
parent_rate = *best_parent_rate;
|
2015-01-19 19:05:29 -07:00
|
|
|
bestdiv = _div_round(table, parent_rate, rate, flags);
|
2012-03-16 00:11:20 -06:00
|
|
|
bestdiv = bestdiv == 0 ? 1 : bestdiv;
|
|
|
|
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
|
|
|
|
return bestdiv;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The maximum divider we can use without overflowing
|
|
|
|
* unsigned long in rate * i below
|
|
|
|
*/
|
|
|
|
maxdiv = min(ULONG_MAX / rate, maxdiv);
|
|
|
|
|
2016-01-04 20:43:41 -07:00
|
|
|
for (i = _next_div(table, 0, flags); i <= maxdiv;
|
|
|
|
i = _next_div(table, i, flags)) {
|
2013-06-02 08:20:55 -06:00
|
|
|
if (rate * i == parent_rate_saved) {
|
|
|
|
/*
|
|
|
|
* It's the most ideal case if the requested rate can be
|
|
|
|
* divided from parent clock without needing to change
|
|
|
|
* parent rate, so return the divider immediately.
|
|
|
|
*/
|
|
|
|
*best_parent_rate = parent_rate_saved;
|
|
|
|
return i;
|
|
|
|
}
|
2015-07-30 18:20:57 -06:00
|
|
|
parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
|
2015-02-21 03:40:23 -07:00
|
|
|
rate * i);
|
2015-04-13 17:03:21 -06:00
|
|
|
now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
|
2015-01-19 19:05:29 -07:00
|
|
|
if (_is_best_div(rate, now, best, flags)) {
|
2012-03-16 00:11:20 -06:00
|
|
|
bestdiv = i;
|
|
|
|
best = now;
|
|
|
|
*best_parent_rate = parent_rate;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!bestdiv) {
|
2015-01-19 19:05:29 -07:00
|
|
|
bestdiv = _get_maxdiv(table, width, flags);
|
2015-07-30 18:20:57 -06:00
|
|
|
*best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
|
2012-03-16 00:11:20 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return bestdiv;
|
|
|
|
}
|
|
|
|
|
2015-01-19 19:05:29 -07:00
|
|
|
long divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate, const struct clk_div_table *table,
|
|
|
|
u8 width, unsigned long flags)
|
2012-03-16 00:11:20 -06:00
|
|
|
{
|
|
|
|
int div;
|
2015-01-19 19:05:29 -07:00
|
|
|
|
|
|
|
div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2015-04-13 17:03:21 -06:00
|
|
|
return DIV_ROUND_UP_ULL((u64)*prate, div);
|
2012-03-16 00:11:20 -06:00
|
|
|
}
|
2015-01-19 19:05:29 -07:00
|
|
|
EXPORT_SYMBOL_GPL(divider_round_rate);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2015-01-19 19:05:29 -07:00
|
|
|
static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate)
|
2012-03-16 00:11:20 -06:00
|
|
|
{
|
|
|
|
struct clk_divider *divider = to_clk_divider(hw);
|
2015-01-19 19:05:29 -07:00
|
|
|
int bestdiv;
|
|
|
|
|
|
|
|
/* if read only, just return current value */
|
|
|
|
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
|
|
|
bestdiv = readl(divider->reg) >> divider->shift;
|
|
|
|
bestdiv &= div_mask(divider->width);
|
2015-05-15 13:45:47 -06:00
|
|
|
bestdiv = _get_div(divider->table, bestdiv, divider->flags,
|
|
|
|
divider->width);
|
2015-04-13 17:03:21 -06:00
|
|
|
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
|
2015-01-19 19:05:29 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return divider_round_rate(hw, rate, prate, divider->table,
|
|
|
|
divider->width, divider->flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
int divider_get_val(unsigned long rate, unsigned long parent_rate,
|
|
|
|
const struct clk_div_table *table, u8 width,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
2012-05-17 04:22:13 -06:00
|
|
|
unsigned int div, value;
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2015-04-13 17:03:21 -06:00
|
|
|
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
|
2014-01-29 09:24:06 -07:00
|
|
|
|
2015-01-19 19:05:29 -07:00
|
|
|
if (!_is_valid_div(table, div, flags))
|
2014-01-29 09:24:06 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2015-05-15 13:45:47 -06:00
|
|
|
value = _get_val(table, div, flags, width);
|
2015-01-19 19:05:29 -07:00
|
|
|
|
|
|
|
return min_t(unsigned int, value, div_mask(width));
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(divider_get_val);
|
|
|
|
|
|
|
|
static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_divider *divider = to_clk_divider(hw);
|
|
|
|
unsigned int value;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
u32 val;
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2015-01-19 19:05:29 -07:00
|
|
|
value = divider_get_val(rate, parent_rate, divider->table,
|
|
|
|
divider->width, divider->flags);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
|
|
|
if (divider->lock)
|
|
|
|
spin_lock_irqsave(divider->lock, flags);
|
2015-07-24 13:21:12 -06:00
|
|
|
else
|
|
|
|
__acquire(divider->lock);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2013-06-08 08:47:18 -06:00
|
|
|
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
|
2015-01-19 19:05:29 -07:00
|
|
|
val = div_mask(divider->width) << (divider->shift + 16);
|
2013-06-08 08:47:18 -06:00
|
|
|
} else {
|
2013-07-22 06:14:40 -06:00
|
|
|
val = clk_readl(divider->reg);
|
2015-01-19 19:05:29 -07:00
|
|
|
val &= ~(div_mask(divider->width) << divider->shift);
|
2013-06-08 08:47:18 -06:00
|
|
|
}
|
2012-05-17 04:22:13 -06:00
|
|
|
val |= value << divider->shift;
|
2013-07-22 06:14:40 -06:00
|
|
|
clk_writel(val, divider->reg);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
|
|
|
if (divider->lock)
|
|
|
|
spin_unlock_irqrestore(divider->lock, flags);
|
2015-07-24 13:21:12 -06:00
|
|
|
else
|
|
|
|
__release(divider->lock);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-27 01:23:22 -06:00
|
|
|
const struct clk_ops clk_divider_ops = {
|
2012-03-16 00:11:20 -06:00
|
|
|
.recalc_rate = clk_divider_recalc_rate,
|
|
|
|
.round_rate = clk_divider_round_rate,
|
|
|
|
.set_rate = clk_divider_set_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_divider_ops);
|
|
|
|
|
2016-01-21 13:53:09 -07:00
|
|
|
const struct clk_ops clk_divider_ro_ops = {
|
|
|
|
.recalc_rate = clk_divider_recalc_rate,
|
|
|
|
.round_rate = clk_divider_round_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
|
|
|
|
|
2016-02-07 00:26:37 -07:00
|
|
|
static struct clk_hw *_register_divider(struct device *dev, const char *name,
|
2012-03-16 00:11:20 -06:00
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
2012-06-29 07:36:32 -06:00
|
|
|
u8 clk_divider_flags, const struct clk_div_table *table,
|
|
|
|
spinlock_t *lock)
|
2012-03-16 00:11:20 -06:00
|
|
|
{
|
|
|
|
struct clk_divider *div;
|
2016-02-07 00:26:37 -07:00
|
|
|
struct clk_hw *hw;
|
2012-04-25 23:58:56 -06:00
|
|
|
struct clk_init_data init;
|
2016-02-07 00:26:37 -07:00
|
|
|
int ret;
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2013-06-08 08:47:18 -06:00
|
|
|
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
|
|
|
|
if (width + shift > 16) {
|
|
|
|
pr_warn("divider value exceeds LOWORD field\n");
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-26 18:51:03 -06:00
|
|
|
/* allocate the divider */
|
2015-05-14 17:47:10 -06:00
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
|
|
if (!div)
|
2012-03-26 18:51:03 -06:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2012-04-25 23:58:56 -06:00
|
|
|
init.name = name;
|
2016-01-21 13:53:09 -07:00
|
|
|
if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
|
|
|
|
init.ops = &clk_divider_ro_ops;
|
|
|
|
else
|
|
|
|
init.ops = &clk_divider_ops;
|
2012-06-01 02:32:47 -06:00
|
|
|
init.flags = flags | CLK_IS_BASIC;
|
2012-04-25 23:58:56 -06:00
|
|
|
init.parent_names = (parent_name ? &parent_name: NULL);
|
|
|
|
init.num_parents = (parent_name ? 1 : 0);
|
|
|
|
|
2012-03-16 00:11:20 -06:00
|
|
|
/* struct clk_divider assignments */
|
|
|
|
div->reg = reg;
|
|
|
|
div->shift = shift;
|
|
|
|
div->width = width;
|
|
|
|
div->flags = clk_divider_flags;
|
|
|
|
div->lock = lock;
|
2012-04-25 23:58:56 -06:00
|
|
|
div->hw.init = &init;
|
2012-06-29 07:36:32 -06:00
|
|
|
div->table = table;
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2012-03-26 18:51:03 -06:00
|
|
|
/* register the clock */
|
2016-02-07 00:26:37 -07:00
|
|
|
hw = &div->hw;
|
|
|
|
ret = clk_hw_register(dev, hw);
|
|
|
|
if (ret) {
|
2012-03-26 18:51:03 -06:00
|
|
|
kfree(div);
|
2016-02-07 00:26:37 -07:00
|
|
|
hw = ERR_PTR(ret);
|
|
|
|
}
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2016-02-07 00:26:37 -07:00
|
|
|
return hw;
|
2012-03-16 00:11:20 -06:00
|
|
|
}
|
2012-06-29 07:36:32 -06:00
|
|
|
|
|
|
|
/**
|
|
|
|
* clk_register_divider - register a divider clock with the clock framework
|
|
|
|
* @dev: device registering this clock
|
|
|
|
* @name: name of this clock
|
|
|
|
* @parent_name: name of clock's parent
|
|
|
|
* @flags: framework-specific flags
|
|
|
|
* @reg: register address to adjust divider
|
|
|
|
* @shift: number of bits to shift the bitfield
|
|
|
|
* @width: width of the bitfield
|
|
|
|
* @clk_divider_flags: divider-specific flags for this clock
|
|
|
|
* @lock: shared register lock for this clock
|
|
|
|
*/
|
|
|
|
struct clk *clk_register_divider(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, spinlock_t *lock)
|
|
|
|
{
|
2016-02-07 00:26:37 -07:00
|
|
|
struct clk_hw *hw;
|
|
|
|
|
|
|
|
hw = _register_divider(dev, name, parent_name, flags, reg, shift,
|
2012-06-29 07:36:32 -06:00
|
|
|
width, clk_divider_flags, NULL, lock);
|
2016-02-07 00:26:37 -07:00
|
|
|
if (IS_ERR(hw))
|
|
|
|
return ERR_CAST(hw);
|
|
|
|
return hw->clk;
|
2012-06-29 07:36:32 -06:00
|
|
|
}
|
2013-08-02 10:14:07 -06:00
|
|
|
EXPORT_SYMBOL_GPL(clk_register_divider);
|
2012-06-29 07:36:32 -06:00
|
|
|
|
2016-02-07 00:26:37 -07:00
|
|
|
/**
|
|
|
|
* clk_hw_register_divider - register a divider clock with the clock framework
|
|
|
|
* @dev: device registering this clock
|
|
|
|
* @name: name of this clock
|
|
|
|
* @parent_name: name of clock's parent
|
|
|
|
* @flags: framework-specific flags
|
|
|
|
* @reg: register address to adjust divider
|
|
|
|
* @shift: number of bits to shift the bitfield
|
|
|
|
* @width: width of the bitfield
|
|
|
|
* @clk_divider_flags: divider-specific flags for this clock
|
|
|
|
* @lock: shared register lock for this clock
|
|
|
|
*/
|
|
|
|
struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, spinlock_t *lock)
|
|
|
|
{
|
|
|
|
return _register_divider(dev, name, parent_name, flags, reg, shift,
|
|
|
|
width, clk_divider_flags, NULL, lock);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(clk_hw_register_divider);
|
|
|
|
|
2012-06-29 07:36:32 -06:00
|
|
|
/**
|
|
|
|
* clk_register_divider_table - register a table based divider clock with
|
|
|
|
* the clock framework
|
|
|
|
* @dev: device registering this clock
|
|
|
|
* @name: name of this clock
|
|
|
|
* @parent_name: name of clock's parent
|
|
|
|
* @flags: framework-specific flags
|
|
|
|
* @reg: register address to adjust divider
|
|
|
|
* @shift: number of bits to shift the bitfield
|
|
|
|
* @width: width of the bitfield
|
|
|
|
* @clk_divider_flags: divider-specific flags for this clock
|
|
|
|
* @table: array of divider/value pairs ending with a div set to 0
|
|
|
|
* @lock: shared register lock for this clock
|
|
|
|
*/
|
|
|
|
struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, const struct clk_div_table *table,
|
|
|
|
spinlock_t *lock)
|
|
|
|
{
|
2016-02-07 00:26:37 -07:00
|
|
|
struct clk_hw *hw;
|
|
|
|
|
|
|
|
hw = _register_divider(dev, name, parent_name, flags, reg, shift,
|
2012-06-29 07:36:32 -06:00
|
|
|
width, clk_divider_flags, table, lock);
|
2016-02-07 00:26:37 -07:00
|
|
|
if (IS_ERR(hw))
|
|
|
|
return ERR_CAST(hw);
|
|
|
|
return hw->clk;
|
2012-06-29 07:36:32 -06:00
|
|
|
}
|
2013-08-02 10:14:07 -06:00
|
|
|
EXPORT_SYMBOL_GPL(clk_register_divider_table);
|
2015-01-05 02:52:40 -07:00
|
|
|
|
2016-02-07 00:26:37 -07:00
|
|
|
/**
|
|
|
|
* clk_hw_register_divider_table - register a table based divider clock with
|
|
|
|
* the clock framework
|
|
|
|
* @dev: device registering this clock
|
|
|
|
* @name: name of this clock
|
|
|
|
* @parent_name: name of clock's parent
|
|
|
|
* @flags: framework-specific flags
|
|
|
|
* @reg: register address to adjust divider
|
|
|
|
* @shift: number of bits to shift the bitfield
|
|
|
|
* @width: width of the bitfield
|
|
|
|
* @clk_divider_flags: divider-specific flags for this clock
|
|
|
|
* @table: array of divider/value pairs ending with a div set to 0
|
|
|
|
* @lock: shared register lock for this clock
|
|
|
|
*/
|
|
|
|
struct clk_hw *clk_hw_register_divider_table(struct device *dev,
|
|
|
|
const char *name, const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, const struct clk_div_table *table,
|
|
|
|
spinlock_t *lock)
|
|
|
|
{
|
|
|
|
return _register_divider(dev, name, parent_name, flags, reg, shift,
|
|
|
|
width, clk_divider_flags, table, lock);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);
|
|
|
|
|
2015-01-05 02:52:40 -07:00
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void clk_unregister_divider(struct clk *clk)
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{
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struct clk_divider *div;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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div = to_clk_divider(hw);
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clk_unregister(clk);
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kfree(div);
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}
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EXPORT_SYMBOL_GPL(clk_unregister_divider);
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2016-02-07 00:26:37 -07:00
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/**
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* clk_hw_unregister_divider - unregister a clk divider
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* @hw: hardware-specific clock data to unregister
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*/
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void clk_hw_unregister_divider(struct clk_hw *hw)
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{
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struct clk_divider *div;
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div = to_clk_divider(hw);
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clk_hw_unregister(hw);
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kfree(div);
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}
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EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);
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