2013-01-31 07:50:12 -07:00
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/*
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* Device Tree file for Marvell Armada XP development board
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* (DB-MV784MP-GP)
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*
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2014-03-04 09:37:01 -07:00
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* Copyright (C) 2013-2014 Marvell
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2013-01-31 07:50:12 -07:00
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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2015-01-26 07:16:03 -07:00
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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2016-12-27 14:36:42 -07:00
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* This file is distributed in the hope that it will be useful,
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2015-01-26 07:16:03 -07:00
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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2016-12-27 14:36:42 -07:00
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* Or, alternatively,
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2015-01-26 07:16:03 -07:00
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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2016-12-27 14:36:42 -07:00
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* restriction, including without limitation the rights to use,
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2015-01-26 07:16:03 -07:00
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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2016-12-27 14:36:42 -07:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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2015-01-26 07:16:03 -07:00
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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2016-12-27 14:36:42 -07:00
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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2015-01-26 07:16:03 -07:00
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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2014-03-04 09:37:01 -07:00
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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2013-01-31 07:50:12 -07:00
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*/
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/dts-v1/;
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2014-11-21 09:00:11 -07:00
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#include <dt-bindings/gpio/gpio.h>
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2013-07-26 07:17:56 -06:00
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#include "armada-xp-mv78460.dtsi"
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2013-01-31 07:50:12 -07:00
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/ {
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model = "Marvell Armada XP Development Board DB-MV784MP-GP";
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compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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2015-03-03 07:41:02 -07:00
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stdout-path = "serial0:115200n8";
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2013-01-31 07:50:12 -07:00
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};
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2016-11-06 01:29:35 -07:00
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memory@0 {
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2013-01-31 07:50:12 -07:00
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device_type = "memory";
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/*
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2013-04-12 08:29:10 -06:00
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* 8 GB of plug-in RAM modules by default.The amount
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* of memory available can be changed by the
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* bootloader according the size of the module
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2014-03-04 09:37:01 -07:00
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* actually plugged. However, memory between
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* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
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* the address range used for I/O (internal registers,
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* MBus windows).
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2013-01-31 07:50:12 -07:00
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*/
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2014-03-04 09:37:01 -07:00
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reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
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2013-04-12 08:29:10 -06:00
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<0x00000001 0x00000000 0x00000001 0x00000000>;
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2013-01-31 07:50:12 -07:00
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};
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2014-11-21 09:00:11 -07:00
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cpus {
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pm_pic {
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ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
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<&gpio0 17 GPIO_ACTIVE_LOW>,
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<&gpio0 18 GPIO_ACTIVE_LOW>;
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};
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};
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2013-01-31 07:50:12 -07:00
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soc {
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2014-03-04 09:37:01 -07:00
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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2013-07-26 07:17:59 -06:00
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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2015-08-18 02:08:53 -06:00
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory window
When the Crypto SRAM mappings were added to the Device Tree files
describing the Armada XP boards in commit c466d997bb16 ("ARM: mvebu:
define crypto SRAM ranges for all armada-xp boards"), the fact that
those mappings were overlaping with the PCIe memory aperture was
overlooked. Due to this, we currently have for all Armada XP platforms
a situation that looks like this:
Memory mapping on Armada XP boards with internal registers at
0xf1000000:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf8000000 -> 0xffe0000 126M PCIe memory aperture
- 0xf8100000 -> 0xf8110000 64KB Crypto SRAM #0 => OVERLAPS WITH PCIE !
- 0xf8110000 -> 0xf8120000 64KB Crypto SRAM #1 => OVERLAPS WITH PCIE !
- 0xffe00000 -> 0xfff00000 1M PCIe I/O aperture
- 0xfff0000 -> 0xffffffff 1M BootROM
The overlap means that when PCIe devices are added, depending on their
memory window needs, they might or might not be mapped into the
physical address space. Indeed, they will not be mapped if the area
allocated in the PCIe memory aperture by the PCI core overlaps with
one of the Crypto SRAM. Typically, a Intel IGB PCIe NIC that needs 8MB
of PCIe memory will see its PCIe memory window allocated from
0xf80000000 for 8MB, which overlaps with the Crypto SRAM windows. Due
to this, the PCIe window is not created, and any attempt to access the
PCIe window makes the kernel explode:
[ 3.302213] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.307841] pci 0000:00:09.0: enabling device (0140 -> 0143)
[ 3.313539] mvebu_mbus: cannot add window '4:f8', conflicts with another window
[ 3.320870] mvebu-pcie soc:pcie-controller: Could not create MBus window at [mem 0xf8000000-0xf87fffff]: -22
[ 3.330811] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf08c0018
This problem does not occur on Armada 370 boards, because we use the
following memory mapping (for boards that have internal registers at
0xf1000000):
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 => OK !
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Obviously, the solution is to align the location of the Crypto SRAM
mappings of Armada XP to be similar with the ones on Armada 370, i.e
have them between the "internal registers" area and the beginning of
the PCIe aperture.
However, we have a special case with the OpenBlocks AX3-4 platform,
which has a 128 MB NOR flash. Currently, this NOR flash is mapped from
0xf0000000 to 0xf8000000. This is possible because on OpenBlocks
AX3-4, the internal registers are not at 0xf1000000. And this explains
why the Crypto SRAM mappings were not configured at the same place on
Armada XP.
Hence, the solution is two-fold:
(1) Move the NOR flash mapping on Armada XP OpenBlocks AX3-4 from
0xe8000000 to 0xf0000000. This frees the 0xf0000000 ->
0xf80000000 space.
(2) Move the Crypto SRAM mappings on Armada XP to be similar to
Armada 370 (except of course that Armada XP has two Crypto SRAM
and not one).
After this patch, the memory mapping on Armada XP boards with
registers at 0xf1 is:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
And the memory mapping for the special case of the OpenBlocks AX3-4
(internal registers at 0xd0000000, NOR of 128 MB):
- 0x00000000 -> 0xc0000000 3G RAM
- 0xd0000000 -> 0xd1000000 1M internal registers
- 0xe800000 -> 0xf0000000 128M NOR flash
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Fixes: c466d997bb16 ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards")
Reported-by: Phil Sutter <phil@nwl.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-08 08:59:57 -07:00
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:
"Highlights:
1) Support more Realtek wireless chips, from Jes Sorenson.
2) New BPF types for per-cpu hash and arrap maps, from Alexei
Starovoitov.
3) Make several TCP sysctls per-namespace, from Nikolay Borisov.
4) Allow the use of SO_REUSEPORT in order to do per-thread processing
of incoming TCP/UDP connections. The muxing can be done using a
BPF program which hashes the incoming packet. From Craig Gallek.
5) Add a multiplexer for TCP streams, to provide a messaged based
interface. BPF programs can be used to determine the message
boundaries. From Tom Herbert.
6) Add 802.1AE MACSEC support, from Sabrina Dubroca.
7) Avoid factorial complexity when taking down an inetdev interface
with lots of configured addresses. We were doing things like
traversing the entire address less for each address removed, and
flushing the entire netfilter conntrack table for every address as
well.
8) Add and use SKB bulk free infrastructure, from Jesper Brouer.
9) Allow offloading u32 classifiers to hardware, and implement for
ixgbe, from John Fastabend.
10) Allow configuring IRQ coalescing parameters on a per-queue basis,
from Kan Liang.
11) Extend ethtool so that larger link mode masks can be supported.
From David Decotigny.
12) Introduce devlink, which can be used to configure port link types
(ethernet vs Infiniband, etc.), port splitting, and switch device
level attributes as a whole. From Jiri Pirko.
13) Hardware offload support for flower classifiers, from Amir Vadai.
14) Add "Local Checksum Offload". Basically, for a tunneled packet
the checksum of the outer header is 'constant' (because with the
checksum field filled into the inner protocol header, the payload
of the outer frame checksums to 'zero'), and we can take advantage
of that in various ways. From Edward Cree"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1548 commits)
bonding: fix bond_get_stats()
net: bcmgenet: fix dma api length mismatch
net/mlx4_core: Fix backward compatibility on VFs
phy: mdio-thunder: Fix some Kconfig typos
lan78xx: add ndo_get_stats64
lan78xx: handle statistics counter rollover
RDS: TCP: Remove unused constant
RDS: TCP: Add sysctl tunables for sndbuf/rcvbuf on rds-tcp socket
net: smc911x: convert pxa dma to dmaengine
team: remove duplicate set of flag IFF_MULTICAST
bonding: remove duplicate set of flag IFF_MULTICAST
net: fix a comment typo
ethernet: micrel: fix some error codes
ip_tunnels, bpf: define IP_TUNNEL_OPTS_MAX and use it
bpf, dst: add and use dst_tclassid helper
bpf: make skb->tc_classid also readable
net: mvneta: bm: clarify dependencies
cls_bpf: reset class and reuse major in da
ldmvsw: Checkpatch sunvnet.c and sunvnet_common.c
ldmvsw: Add ldmvsw.c driver code
...
2016-03-19 11:05:34 -06:00
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
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2016-03-14 02:39:00 -06:00
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MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
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2013-07-26 07:17:59 -06:00
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devbus-bootcs {
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status = "okay";
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/* Device Bus parameters are required */
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/* Read parameters */
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2014-04-14 09:29:19 -06:00
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devbus,bus-width = <16>;
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2013-07-26 07:17:59 -06:00
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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};
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2013-05-17 05:09:57 -06:00
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2013-04-12 08:29:09 -06:00
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internal-regs {
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serial@12000 {
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status = "okay";
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2013-01-31 07:50:12 -07:00
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};
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2013-04-12 08:29:09 -06:00
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serial@12100 {
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status = "okay";
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2013-01-31 07:50:12 -07:00
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};
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2013-04-12 08:29:09 -06:00
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serial@12200 {
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status = "okay";
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};
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serial@12300 {
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status = "okay";
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2013-01-31 07:50:12 -07:00
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};
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2014-11-21 09:00:11 -07:00
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pinctrl {
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pinctrl-0 = <&pic_pins>;
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pinctrl-names = "default";
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pic_pins: pic-pins-0 {
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marvell,pins = "mpp16", "mpp17",
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"mpp18";
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marvell,function = "gpio";
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};
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};
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2013-04-12 08:29:09 -06:00
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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2013-01-31 07:50:12 -07:00
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};
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2013-04-12 08:29:09 -06:00
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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2014-04-15 07:50:21 -06:00
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phy-mode = "qsgmii";
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2016-03-14 02:39:00 -06:00
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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2013-04-12 08:29:09 -06:00
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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2014-04-15 07:50:21 -06:00
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phy-mode = "qsgmii";
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2016-03-14 02:39:00 -06:00
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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2013-04-12 08:29:09 -06:00
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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2014-04-15 07:50:21 -06:00
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phy-mode = "qsgmii";
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2016-03-14 02:39:00 -06:00
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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2013-04-12 08:29:09 -06:00
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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2014-04-15 07:50:21 -06:00
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phy-mode = "qsgmii";
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2016-03-14 02:39:00 -06:00
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buffer-manager = <&bm>;
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bm,pool-long = <3>;
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2013-04-12 08:29:09 -06:00
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};
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2013-04-09 15:06:39 -06:00
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2013-05-21 11:53:09 -06:00
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/* Front-side USB slot */
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usb@50000 {
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status = "okay";
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};
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/* Back-side USB slot */
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usb@51000 {
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status = "okay";
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};
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2016-03-14 02:39:00 -06:00
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bm@c0000 {
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status = "okay";
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};
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2013-11-07 08:17:34 -07:00
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nand@d0000 {
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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};
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2013-04-09 15:06:39 -06:00
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};
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2016-03-14 02:39:00 -06:00
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bm-bppi {
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status = "okay";
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};
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2013-01-31 07:50:12 -07:00
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};
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};
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2016-07-13 03:55:18 -06:00
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|
|
2016-11-05 12:03:50 -06:00
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|
|
&pciec {
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|
|
|
status = "okay";
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The 3 slots are physically present as
|
|
|
|
* standard PCIe slots on the board.
|
|
|
|
*/
|
|
|
|
pcie@1,0 {
|
|
|
|
/* Port 0, Lane 0 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
pcie@9,0 {
|
|
|
|
/* Port 2, Lane 0 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
pcie@10,0 {
|
|
|
|
/* Port 3, Lane 0 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2016-11-04 10:54:54 -06:00
|
|
|
&mdio {
|
|
|
|
phy0: ethernet-phy@0 {
|
|
|
|
reg = <16>;
|
|
|
|
};
|
|
|
|
|
|
|
|
phy1: ethernet-phy@1 {
|
|
|
|
reg = <17>;
|
|
|
|
};
|
|
|
|
|
|
|
|
phy2: ethernet-phy@2 {
|
|
|
|
reg = <18>;
|
|
|
|
};
|
|
|
|
|
|
|
|
phy3: ethernet-phy@3 {
|
|
|
|
reg = <19>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2016-07-13 03:55:18 -06:00
|
|
|
&spi0 {
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
spi-flash@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
compatible = "n25q128a13", "jedec,spi-nor";
|
|
|
|
reg = <0>; /* Chip select 0 */
|
|
|
|
spi-max-frequency = <108000000>;
|
|
|
|
};
|
|
|
|
};
|