2015-02-16 05:31:04 -07:00
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/*
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* Device Tree file for the Linksys WRT1900AC (Mamba).
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*
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* Note: this board is shipped with a new generation boot loader that
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* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
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* is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be
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* used.
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*
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* Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on armada-xp-axpwifiap.dts:
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*
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* Copyright (C) 2013 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "armada-xp-mv78230.dtsi"
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/ {
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model = "Linksys WRT1900AC";
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compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
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"marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200";
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stdout-path = &uart0;
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};
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2016-11-06 01:29:35 -07:00
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memory@0 {
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2015-02-16 05:31:04 -07:00
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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2015-08-18 02:08:53 -06:00
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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ARM: mvebu: fix overlap of Crypto SRAM with PCIe memory window
When the Crypto SRAM mappings were added to the Device Tree files
describing the Armada XP boards in commit c466d997bb16 ("ARM: mvebu:
define crypto SRAM ranges for all armada-xp boards"), the fact that
those mappings were overlaping with the PCIe memory aperture was
overlooked. Due to this, we currently have for all Armada XP platforms
a situation that looks like this:
Memory mapping on Armada XP boards with internal registers at
0xf1000000:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf8000000 -> 0xffe0000 126M PCIe memory aperture
- 0xf8100000 -> 0xf8110000 64KB Crypto SRAM #0 => OVERLAPS WITH PCIE !
- 0xf8110000 -> 0xf8120000 64KB Crypto SRAM #1 => OVERLAPS WITH PCIE !
- 0xffe00000 -> 0xfff00000 1M PCIe I/O aperture
- 0xfff0000 -> 0xffffffff 1M BootROM
The overlap means that when PCIe devices are added, depending on their
memory window needs, they might or might not be mapped into the
physical address space. Indeed, they will not be mapped if the area
allocated in the PCIe memory aperture by the PCI core overlaps with
one of the Crypto SRAM. Typically, a Intel IGB PCIe NIC that needs 8MB
of PCIe memory will see its PCIe memory window allocated from
0xf80000000 for 8MB, which overlaps with the Crypto SRAM windows. Due
to this, the PCIe window is not created, and any attempt to access the
PCIe window makes the kernel explode:
[ 3.302213] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.307841] pci 0000:00:09.0: enabling device (0140 -> 0143)
[ 3.313539] mvebu_mbus: cannot add window '4:f8', conflicts with another window
[ 3.320870] mvebu-pcie soc:pcie-controller: Could not create MBus window at [mem 0xf8000000-0xf87fffff]: -22
[ 3.330811] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf08c0018
This problem does not occur on Armada 370 boards, because we use the
following memory mapping (for boards that have internal registers at
0xf1000000):
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0 => OK !
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Obviously, the solution is to align the location of the Crypto SRAM
mappings of Armada XP to be similar with the ones on Armada 370, i.e
have them between the "internal registers" area and the beginning of
the PCIe aperture.
However, we have a special case with the OpenBlocks AX3-4 platform,
which has a 128 MB NOR flash. Currently, this NOR flash is mapped from
0xf0000000 to 0xf8000000. This is possible because on OpenBlocks
AX3-4, the internal registers are not at 0xf1000000. And this explains
why the Crypto SRAM mappings were not configured at the same place on
Armada XP.
Hence, the solution is two-fold:
(1) Move the NOR flash mapping on Armada XP OpenBlocks AX3-4 from
0xe8000000 to 0xf0000000. This frees the 0xf0000000 ->
0xf80000000 space.
(2) Move the Crypto SRAM mappings on Armada XP to be similar to
Armada 370 (except of course that Armada XP has two Crypto SRAM
and not one).
After this patch, the memory mapping on Armada XP boards with
registers at 0xf1 is:
- 0x00000000 -> 0xf0000000 3.75G RAM
- 0xf0000000 -> 0xf1000000 16M NOR flashes (AXP GP / AXP DB)
- 0xf1000000 -> 0xf1100000 1M internal registers
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
And the memory mapping for the special case of the OpenBlocks AX3-4
(internal registers at 0xd0000000, NOR of 128 MB):
- 0x00000000 -> 0xc0000000 3G RAM
- 0xd0000000 -> 0xd1000000 1M internal registers
- 0xe800000 -> 0xf0000000 128M NOR flash
- 0xf1100000 -> 0xf1110000 64KB Crypto SRAM #0
- 0xf1110000 -> 0xf1120000 64KB Crypto SRAM #1
- 0xf8000000 -> 0xffe0000 126M PCIe memory
- 0xffe00000 -> 0xfff00000 1M PCIe I/O
- 0xfff0000 -> 0xffffffff 1M BootROM
Fixes: c466d997bb16 ("ARM: mvebu: define crypto SRAM ranges for all armada-xp boards")
Reported-by: Phil Sutter <phil@nwl.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: <stable@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-08 08:59:57 -07:00
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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2015-02-16 05:31:04 -07:00
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internal-regs {
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2015-05-20 15:22:04 -06:00
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rtc@10300 {
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/* No crystal connected to the internal RTC */
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status = "disabled";
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};
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2015-02-16 05:31:04 -07:00
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/* J10: VCC, NC, RX, NC, TX, GND */
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serial@12000 {
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <1>;
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status = "okay";
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};
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ethernet@70000 {
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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status = "okay";
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet@74000 {
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pinctrl-0 = <&ge1_rgmii_pins>;
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pinctrl-names = "default";
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status = "okay";
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* USB part of the eSATA/USB 2.0 port */
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usb@50000 {
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status = "okay";
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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tmp421@4c {
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compatible = "ti,tmp421";
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reg = <0x4c>;
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};
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tlc59116@68 {
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#address-cells = <1>;
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#size-cells = <0>;
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#gpio-cells = <2>;
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compatible = "ti,tlc59116";
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reg = <0x68>;
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wan_amber@0 {
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label = "mamba:amber:wan";
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reg = <0x0>;
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};
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wan_white@1 {
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label = "mamba:white:wan";
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reg = <0x1>;
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};
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wlan_2g@2 {
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label = "mamba:white:wlan_2g";
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reg = <0x2>;
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};
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wlan_5g@3 {
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label = "mamba:white:wlan_5g";
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reg = <0x3>;
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};
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esata@4 {
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label = "mamba:white:esata";
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reg = <0x4>;
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};
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usb2@5 {
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label = "mamba:white:usb2";
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reg = <0x5>;
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};
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usb3_1@6 {
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label = "mamba:white:usb3_1";
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reg = <0x6>;
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};
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usb3_2@7 {
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label = "mamba:white:usb3_2";
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reg = <0x7>;
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};
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wps_white@8 {
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label = "mamba:white:wps";
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reg = <0x8>;
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};
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wps_amber@9 {
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label = "mamba:amber:wps";
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reg = <0x9>;
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};
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};
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};
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nand@d0000 {
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x100000>; /* 1MB */
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read-only;
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};
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partition@100000 {
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label = "u_env";
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reg = <0x100000 0x40000>; /* 256KB */
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};
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partition@140000 {
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label = "s_env";
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reg = <0x140000 0x40000>; /* 256KB */
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};
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partition@900000 {
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label = "devinfo";
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reg = <0x900000 0x100000>; /* 1MB */
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read-only;
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};
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/* kernel1 overlaps with rootfs1 by design */
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partition@a00000 {
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label = "kernel1";
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reg = <0xa00000 0x2800000>; /* 40MB */
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};
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partition@d00000 {
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label = "rootfs1";
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reg = <0xd00000 0x2500000>; /* 37MB */
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};
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/* kernel2 overlaps with rootfs2 by design */
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partition@3200000 {
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label = "kernel2";
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reg = <0x3200000 0x2800000>; /* 40MB */
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};
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partition@3500000 {
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label = "rootfs2";
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reg = <0x3500000 0x2500000>; /* 37MB */
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};
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/*
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* 38MB, last MB is for the BBT, not writable
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*/
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partition@5a00000 {
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label = "syscfg";
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reg = <0x5a00000 0x2600000>;
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};
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/*
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* Unused area between "s_env" and "devinfo".
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* Moved here because otherwise the renumbered
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* partitions would break the bootloader
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* supplied bootargs
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*/
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partition@180000 {
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label = "unused_area";
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reg = <0x180000 0x780000>; /* 7.5MB */
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};
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};
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&keys_pin>;
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pinctrl-names = "default";
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2016-11-06 02:59:19 -07:00
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wps {
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2015-02-16 05:31:04 -07:00
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label = "WPS";
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linux,code = <KEY_WPS_BUTTON>;
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2015-07-31 12:42:00 -06:00
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gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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2015-02-16 05:31:04 -07:00
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};
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2016-11-06 02:59:19 -07:00
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reset {
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2015-02-16 05:31:04 -07:00
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label = "Factory Reset Button";
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linux,code = <KEY_RESTART>;
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2015-07-31 12:42:00 -06:00
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gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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2015-02-16 05:31:04 -07:00
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&power_led_pin>;
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pinctrl-names = "default";
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power {
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label = "mamba:white:power";
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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gpio_fan {
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/* SUNON HA4010V4-0000-C99 */
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compatible = "gpio-fan";
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gpios = <&gpio0 24 0>;
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gpio-fan,speed-map = <0 0
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4500 1>;
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};
|
2015-02-28 13:20:48 -07:00
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2016-11-06 02:35:41 -07:00
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dsa {
|
2017-01-17 11:22:20 -07:00
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status = "disabled";
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2015-02-28 13:20:48 -07:00
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compatible = "marvell,dsa";
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#address-cells = <2>;
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#size-cells = <0>;
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dsa,ethernet = <ð0>;
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|
|
dsa,mii-bus = <&mdio>;
|
|
|
|
|
|
|
|
switch@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
reg = <0>;
|
|
|
|
label = "lan4";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
reg = <1>;
|
|
|
|
label = "lan3";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@2 {
|
|
|
|
reg = <2>;
|
|
|
|
label = "lan2";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@3 {
|
|
|
|
reg = <3>;
|
|
|
|
label = "lan1";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@4 {
|
|
|
|
reg = <4>;
|
|
|
|
label = "internet";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@5 {
|
|
|
|
reg = <5>;
|
|
|
|
label = "cpu";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
2015-02-16 05:31:04 -07:00
|
|
|
};
|
|
|
|
|
2016-11-05 12:03:50 -06:00
|
|
|
&pciec {
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
/* Etron EJ168 USB 3.0 controller */
|
|
|
|
pcie@1,0 {
|
|
|
|
/* Port 0, Lane 0 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
/* First mini-PCIe port */
|
|
|
|
pcie@2,0 {
|
|
|
|
/* Port 0, Lane 1 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Second mini-PCIe port */
|
|
|
|
pcie@3,0 {
|
|
|
|
/* Port 0, Lane 3 */
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2015-02-16 05:31:04 -07:00
|
|
|
&pinctrl {
|
|
|
|
|
|
|
|
keys_pin: keys-pin {
|
|
|
|
marvell,pins = "mpp32", "mpp33";
|
|
|
|
marvell,function = "gpio";
|
|
|
|
};
|
|
|
|
|
|
|
|
power_led_pin: power-led-pin {
|
|
|
|
marvell,pins = "mpp40";
|
|
|
|
marvell,function = "gpio";
|
|
|
|
};
|
|
|
|
|
|
|
|
gpio_fan_pin: gpio-fan-pin {
|
|
|
|
marvell,pins = "mpp24";
|
|
|
|
marvell,function = "gpio";
|
|
|
|
};
|
|
|
|
};
|
2016-07-13 03:55:18 -06:00
|
|
|
|
|
|
|
&spi0 {
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
spi-flash@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
compatible = "everspin,mr25h256";
|
|
|
|
reg = <0>; /* Chip select 0 */
|
|
|
|
spi-max-frequency = <40000000>;
|
|
|
|
};
|
|
|
|
};
|
2017-01-17 11:22:20 -07:00
|
|
|
|
|
|
|
&mdio {
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
switch@0 {
|
|
|
|
compatible = "marvell,mv88e6085";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
reg = <0>;
|
|
|
|
label = "lan4";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
reg = <1>;
|
|
|
|
label = "lan3";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@2 {
|
|
|
|
reg = <2>;
|
|
|
|
label = "lan2";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@3 {
|
|
|
|
reg = <3>;
|
|
|
|
label = "lan1";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@4 {
|
|
|
|
reg = <4>;
|
|
|
|
label = "internet";
|
|
|
|
};
|
|
|
|
|
|
|
|
port@5 {
|
|
|
|
reg = <5>;
|
|
|
|
label = "cpu";
|
|
|
|
ethernet = <ð0>;
|
|
|
|
fixed-link {
|
|
|
|
speed = <1000>;
|
|
|
|
full-duplex;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|