2014-04-14 09:37:23 -06:00
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/*
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* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2014-04-14 09:37:26 -06:00
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#include <dt-bindings/gpio/gpio.h>
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2014-04-14 09:37:23 -06:00
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/ {
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2015-10-13 05:43:55 -06:00
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model = "Phytec phyFLEX-i.MX6 Quad";
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2014-04-14 09:37:23 -06:00
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compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
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memory {
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reg = <0x10000000 0x80000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 15 0>;
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2015-04-21 07:59:53 -06:00
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enable-active-high;
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2014-04-14 09:37:23 -06:00
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};
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reg_usb_h1_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 0 0>;
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2015-04-21 07:59:53 -06:00
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enable-active-high;
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2014-04-14 09:37:23 -06:00
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};
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};
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2014-04-14 09:37:25 -06:00
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gpio_leds: leds {
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compatible = "gpio-leds";
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green {
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label = "phyflex:green";
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gpios = <&gpio1 30 0>;
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};
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red {
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label = "phyflex:red";
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gpios = <&gpio2 31 0>;
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};
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};
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2014-04-14 09:37:23 -06:00
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};
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2014-11-04 06:05:48 -07:00
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "disabled";
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};
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2014-11-14 06:32:26 -07:00
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "disabled";
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};
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2014-04-14 09:37:23 -06:00
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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status = "okay";
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cs-gpios = <&gpio4 24 0>;
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flash@0 {
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2015-08-16 00:39:17 -06:00
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compatible = "m25p80", "jedec,spi-nor";
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2014-04-14 09:37:23 -06:00
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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2014-11-14 06:32:22 -07:00
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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phy-supply = <&vdd_eth_io_reg>;
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status = "disabled";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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2014-11-14 06:32:23 -07:00
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status = "okay";
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2014-11-14 06:32:22 -07:00
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};
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2014-04-14 09:37:23 -06:00
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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pmic@58 {
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2014-08-22 08:26:55 -06:00
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compatible = "dlg,da9063";
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2014-04-14 09:37:23 -06:00
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reg = <0x58>;
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2014-11-14 06:32:24 -07:00
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interrupt-parent = <&gpio2>;
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interrupts = <9 0x8>; /* active-low GPIO2_9 */
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2014-04-14 09:37:23 -06:00
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regulators {
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vddcore_reg: bcore1 {
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regulator-min-microvolt = <730000>;
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regulator-max-microvolt = <1380000>;
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regulator-always-on;
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};
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vddsoc_reg: bcore2 {
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regulator-min-microvolt = <730000>;
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regulator-max-microvolt = <1380000>;
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regulator-always-on;
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};
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vdd_ddr3_reg: bpro {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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};
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vdd_3v3_reg: bperi {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vdd_buckmem_reg: bmem {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vdd_eth_reg: bio {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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vdd_eth_io_reg: ldo4 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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vdd_mx6_snvs_reg: ldo5 {
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vdd_3v3_pmic_io_reg: ldo6 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vdd_sd0_reg: ldo9 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_sd1_reg: ldo10 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_mx6_high_reg: ldo11 {
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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};
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};
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};
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2014-11-04 06:05:47 -07:00
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <100000>;
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <100000>;
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};
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2014-04-14 09:37:23 -06:00
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx6q-phytec-pfla02 {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
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MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
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2014-11-14 06:32:24 -07:00
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MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
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2014-04-14 09:37:25 -06:00
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
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MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
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2014-04-14 09:37:23 -06:00
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>;
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};
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
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MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
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MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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2016-07-08 15:22:54 -06:00
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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2014-04-14 09:37:23 -06:00
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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2016-07-08 15:22:54 -06:00
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
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2014-04-14 09:37:23 -06:00
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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>;
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};
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2014-11-14 06:32:26 -07:00
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
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MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
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>;
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};
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2014-04-14 09:37:23 -06:00
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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2014-11-04 06:05:47 -07:00
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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2014-11-14 06:32:25 -07:00
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pinctrl_pcie: pciegrp {
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fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
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};
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2014-04-14 09:37:30 -06:00
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
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MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
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>;
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};
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2014-04-14 09:37:23 -06:00
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
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MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usbh1: usbh1grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
|
|
|
|
>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
|
|
fsl,pins = <
|
|
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
|
|
|
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
|
|
|
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
|
|
|
|
>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
|
|
fsl,pins = <
|
|
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
|
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
|
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
|
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
|
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
|
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
|
|
|
>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
|
|
fsl,pins = <
|
|
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
|
|
>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl_usdhc3_cdwp: usdhc3cdwp {
|
|
|
|
fsl,pins = <
|
|
|
|
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
|
|
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
|
|
|
>;
|
|
|
|
};
|
2014-11-04 06:05:48 -07:00
|
|
|
|
|
|
|
pinctrl_audmux: audmuxgrp {
|
|
|
|
fsl,pins = <
|
|
|
|
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
|
|
|
|
MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
|
|
|
|
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
|
|
|
|
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
|
|
|
|
>;
|
|
|
|
};
|
2014-04-14 09:37:23 -06:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2014-11-14 06:32:25 -07:00
|
|
|
&pcie {
|
2015-10-13 05:43:55 -06:00
|
|
|
pinctrl-names = "default";
|
2014-11-14 06:32:25 -07:00
|
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
|
|
reset-gpio = <&gpio4 17 0>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2016-07-14 04:30:34 -06:00
|
|
|
®_arm {
|
|
|
|
vin-supply = <&vddcore_reg>;
|
|
|
|
};
|
|
|
|
|
|
|
|
®_pu {
|
|
|
|
vin-supply = <&vddsoc_reg>;
|
|
|
|
};
|
|
|
|
|
|
|
|
®_soc {
|
|
|
|
vin-supply = <&vddsoc_reg>;
|
|
|
|
};
|
|
|
|
|
2014-04-14 09:37:30 -06:00
|
|
|
&uart3 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2014-04-14 09:37:23 -06:00
|
|
|
&uart4 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_uart4>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usbh1 {
|
|
|
|
vbus-supply = <®_usb_h1_vbus>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usbh1>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usbotg {
|
|
|
|
vbus-supply = <®_usb_otg_vbus>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
|
|
disable-over-current;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usdhc2 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
2015-07-22 06:53:02 -06:00
|
|
|
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
|
|
|
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
2014-04-14 09:37:23 -06:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usdhc3 {
|
2016-10-14 03:39:29 -06:00
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usdhc3
|
2014-04-14 09:37:23 -06:00
|
|
|
&pinctrl_usdhc3_cdwp>;
|
2015-07-22 06:53:02 -06:00
|
|
|
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
|
|
|
|
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
2016-10-14 03:39:29 -06:00
|
|
|
status = "disabled";
|
2014-04-14 09:37:23 -06:00
|
|
|
};
|