2012-03-16 00:11:19 -06:00
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/*
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* linux/include/linux/clk-provider.h
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*
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* Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_CLK_PROVIDER_H
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#define __LINUX_CLK_PROVIDER_H
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#include <linux/clk.h>
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#include <linux/io.h>
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#ifdef CONFIG_COMMON_CLK
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/*
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* flags used across common struct clk. these flags should only affect the
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* top-level framework. custom flags for dealing with hardware specifics
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* belong in struct clk_foo
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*/
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#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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2012-08-31 06:21:28 -06:00
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
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struct clk_hw;
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struct dentry;
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2012-03-16 00:11:19 -06:00
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/**
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* struct clk_ops - Callback operations for hardware clocks; these are to
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* be provided by the clock implementation, and will be called by drivers
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* through the clk_* api.
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*
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* @prepare: Prepare the clock for enabling. This must not return until
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* the clock is fully prepared, and it's safe to call clk_enable.
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* This callback is intended to allow clock implementations to
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* do any initialisation that may sleep. Called with
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* prepare_lock held.
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*
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* @unprepare: Release the clock from its prepared state. This will typically
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* undo any work done in the @prepare callback. Called with
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* prepare_lock held.
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*
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* @is_prepared: Queries the hardware to determine if the clock is prepared.
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* This function is allowed to sleep. Optional, if this op is not
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* set then the prepare count will be used.
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*
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* @unprepare_unused: Unprepare the clock atomically. Only called from
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* clk_disable_unused for prepare clocks with special needs.
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* Called with prepare mutex held. This function may sleep.
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*
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* @enable: Enable the clock atomically. This must not return until the
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* clock is generating a valid clock signal, usable by consumer
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* devices. Called with enable_lock held. This function must not
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* sleep.
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*
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* @disable: Disable the clock atomically. Called with enable_lock held.
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* This function must not sleep.
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*
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* @is_enabled: Queries the hardware to determine if the clock is enabled.
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* This function must not sleep. Optional, if this op is not
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* set then the enable count will be used.
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*
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* @disable_unused: Disable the clock atomically. Only called from
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* clk_disable_unused for gate clocks with special needs.
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* Called with enable_lock held. This function must not
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* sleep.
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*
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* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
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* parent rate is an input parameter. It is up to the caller to
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* ensure that the prepare_mutex is held across this call.
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* Returns the calculated rate. Optional, but recommended - if
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* this op is not set then clock rate will be initialized to 0.
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*
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* @round_rate: Given a target rate as input, returns the closest rate actually
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* supported by the clock.
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*
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* @determine_rate: Given a target rate as input, returns the closest rate
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* actually supported by the clock, and optionally the parent clock
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* that should be used to provide the clock rate.
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*
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* @get_parent: Queries the hardware to determine the parent of a clock. The
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* return value is a u8 which specifies the index corresponding to
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* the parent clock. This index can be applied to either the
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* .parent_names or .parents arrays. In short, this function
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* translates the parent value read from hardware into an array
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* index. Currently only called when the clock is initialized by
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* __clk_init. This callback is mandatory for clocks with
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* multiple parents. It is optional (and unnecessary) for clocks
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* with 0 or 1 parents.
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*
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* @set_parent: Change the input source of this clock; for clocks with multiple
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* possible parents specify a new parent by passing in the index
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* as a u8 corresponding to the parent in either the .parent_names
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* or .parents arrays. This function in affect translates an
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* array index into the value programmed into the hardware.
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* Returns 0 on success, -EERROR otherwise.
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*
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* @set_rate: Change the rate of this clock. The requested rate is specified
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* by the second argument, which should typically be the return
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* of .round_rate call. The third argument gives the parent rate
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* which is likely helpful for most .set_rate implementation.
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* Returns 0 on success, -EERROR otherwise.
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*
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* @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
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* is expressed in ppb (parts per billion). The parent accuracy is
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* an input parameter.
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* Returns the calculated accuracy. Optional - if this op is not
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* set then clock accuracy will be initialized to parent accuracy
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* or 0 (perfect clock) if clock has no parent.
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*
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* @set_rate_and_parent: Change the rate and the parent of this clock. The
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* requested rate is specified by the second argument, which
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* should typically be the return of .round_rate call. The
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* third argument gives the parent rate which is likely helpful
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* for most .set_rate_and_parent implementation. The fourth
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* argument gives the parent index. This callback is optional (and
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* unnecessary) for clocks with 0 or 1 parents as well as
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* for clocks that can tolerate switching the rate and the parent
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* separately via calls to .set_parent and .set_rate.
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* Returns 0 on success, -EERROR otherwise.
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*
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* @debug_init: Set up type-specific debugfs entries for this clock. This
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* is called once, after the debugfs directory entry for this
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* clock has been created. The dentry pointer representing that
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* directory is provided as an argument. Called with
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* prepare_lock held. Returns 0 on success, -EERROR otherwise.
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*
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*
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* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
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* implementations to split any work between atomic (enable) and sleepable
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* (prepare) contexts. If enabling a clock requires code that might sleep,
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* this must be done in clk_prepare. Clock enable code that will never be
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* called in a sleepable context may be implemented in clk_enable.
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*
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* Typically, drivers will call clk_prepare when a clock may be needed later
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* (eg. when a device is opened), and clk_enable when the clock is actually
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* required (eg. from an interrupt). Note that clk_prepare MUST have been
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* called before clk_enable.
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*/
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struct clk_ops {
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int (*prepare)(struct clk_hw *hw);
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void (*unprepare)(struct clk_hw *hw);
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int (*is_prepared)(struct clk_hw *hw);
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void (*unprepare_unused)(struct clk_hw *hw);
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int (*enable)(struct clk_hw *hw);
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void (*disable)(struct clk_hw *hw);
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int (*is_enabled)(struct clk_hw *hw);
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void (*disable_unused)(struct clk_hw *hw);
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unsigned long (*recalc_rate)(struct clk_hw *hw,
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unsigned long parent_rate);
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long (*round_rate)(struct clk_hw *hw, unsigned long,
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unsigned long *);
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long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate,
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struct clk **best_parent_clk);
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int (*set_parent)(struct clk_hw *hw, u8 index);
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u8 (*get_parent)(struct clk_hw *hw);
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int (*set_rate)(struct clk_hw *hw, unsigned long,
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unsigned long);
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int (*set_rate_and_parent)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate, u8 index);
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unsigned long (*recalc_accuracy)(struct clk_hw *hw,
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unsigned long parent_accuracy);
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void (*init)(struct clk_hw *hw);
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int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
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};
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2012-04-25 23:58:56 -06:00
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/**
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* struct clk_init_data - holds init data that's common to all clocks and is
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* shared between the clock provider and the common clock framework.
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*
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* @name: clock name
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* @ops: operations this clock supports
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* @parent_names: array of string names for all possible parents
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* @num_parents: number of possible parents
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* @flags: framework-level hints and quirks
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*/
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struct clk_init_data {
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const char *name;
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const struct clk_ops *ops;
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const char **parent_names;
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u8 num_parents;
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unsigned long flags;
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};
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/**
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* struct clk_hw - handle for traversing from a struct clk to its corresponding
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* hardware-specific structure. struct clk_hw should be declared within struct
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* clk_foo and then referenced by the struct clk instance that uses struct
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* clk_foo's clk_ops
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*
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* @clk: pointer to the struct clk instance that points back to this struct
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* clk_hw instance
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*
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* @init: pointer to struct clk_init_data that contains the init data shared
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* with the common clock framework.
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*/
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struct clk_hw {
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struct clk *clk;
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const struct clk_init_data *init;
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};
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2012-03-16 00:11:20 -06:00
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/*
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* DOC: Basic clock implementations common to many platforms
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*
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* Each basic clock hardware type is comprised of a structure describing the
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* clock hardware, implementations of the relevant callbacks in struct clk_ops,
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* unique flags for that hardware type, a registration function and an
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* alternative macro for static initialization
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*/
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/**
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* struct clk_fixed_rate - fixed-rate clock
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* @hw: handle between common and hardware-specific interfaces
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* @fixed_rate: constant frequency of clock
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*/
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struct clk_fixed_rate {
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struct clk_hw hw;
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unsigned long fixed_rate;
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unsigned long fixed_accuracy;
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u8 flags;
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};
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2012-03-27 01:23:23 -06:00
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extern const struct clk_ops clk_fixed_rate_ops;
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struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned long fixed_rate);
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struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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unsigned long fixed_rate, unsigned long fixed_accuracy);
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2012-04-07 20:39:39 -06:00
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void of_fixed_clk_setup(struct device_node *np);
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2012-03-16 00:11:20 -06:00
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/**
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* struct clk_gate - gating clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling gate
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* @bit_idx: single bit controlling gate
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Clock which can gate its output. Implements .enable & .disable
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*
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* Flags:
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* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
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* enable the clock. Setting this flag does the opposite: setting the bit
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* disable the clock and clearing it enables the clock
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* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
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* of this register, and mask of gate bits are in higher 16-bit of this
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* register. While setting the gate bits, higher 16-bit should also be
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* updated to indicate changing gate bits.
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*/
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struct clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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u8 flags;
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spinlock_t *lock;
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};
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#define CLK_GATE_SET_TO_DISABLE BIT(0)
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#define CLK_GATE_HIWORD_MASK BIT(1)
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2012-03-27 01:23:23 -06:00
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extern const struct clk_ops clk_gate_ops;
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock);
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2012-06-29 07:36:32 -06:00
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struct clk_div_table {
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unsigned int val;
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unsigned int div;
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};
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2012-03-16 00:11:20 -06:00
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/**
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* struct clk_divider - adjustable divider clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing the divider
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* @shift: shift to the divider bit field
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* @width: width of the divider bit field
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* @table: array of value/divider pairs, last entry should have div = 0
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* @lock: register lock
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*
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* Clock with an adjustable divider affecting its output frequency. Implements
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* .recalc_rate, .set_rate and .round_rate
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*
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* Flags:
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* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
|
|
|
|
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
|
|
|
|
* the raw value read from the register, with the value of zero considered
|
2013-04-02 16:36:56 -06:00
|
|
|
* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
|
2012-03-16 00:11:20 -06:00
|
|
|
* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
|
|
|
|
* the hardware register
|
2013-04-02 16:36:56 -06:00
|
|
|
* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
|
|
|
|
* CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
|
|
|
|
* Some hardware implementations gracefully handle this case and allow a
|
|
|
|
* zero divisor by not modifying their input clock
|
|
|
|
* (divide by one / bypass).
|
2013-06-08 08:47:18 -06:00
|
|
|
* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
|
|
|
|
* of this register, and mask of divider bits are in higher 16-bit of this
|
|
|
|
* register. While setting the divider bits, higher 16-bit should also be
|
|
|
|
* updated to indicate changing divider bits.
|
2012-03-16 00:11:20 -06:00
|
|
|
*/
|
|
|
|
struct clk_divider {
|
|
|
|
struct clk_hw hw;
|
|
|
|
void __iomem *reg;
|
|
|
|
u8 shift;
|
|
|
|
u8 width;
|
|
|
|
u8 flags;
|
2012-06-29 07:36:32 -06:00
|
|
|
const struct clk_div_table *table;
|
2012-03-16 00:11:20 -06:00
|
|
|
spinlock_t *lock;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define CLK_DIVIDER_ONE_BASED BIT(0)
|
|
|
|
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
|
2013-04-02 16:36:56 -06:00
|
|
|
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
|
2013-06-08 08:47:18 -06:00
|
|
|
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2012-03-27 01:23:23 -06:00
|
|
|
extern const struct clk_ops clk_divider_ops;
|
2012-03-16 00:11:20 -06:00
|
|
|
struct clk *clk_register_divider(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, spinlock_t *lock);
|
2012-06-29 07:36:32 -06:00
|
|
|
struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_divider_flags, const struct clk_div_table *table,
|
|
|
|
spinlock_t *lock);
|
2012-03-16 00:11:20 -06:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct clk_mux - multiplexer clock
|
|
|
|
*
|
|
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
|
|
* @reg: register controlling multiplexer
|
|
|
|
* @shift: shift to multiplexer bit field
|
|
|
|
* @width: width of mutliplexer bit field
|
2013-03-25 08:35:07 -06:00
|
|
|
* @flags: hardware-specific flags
|
2012-03-16 00:11:20 -06:00
|
|
|
* @lock: register lock
|
|
|
|
*
|
|
|
|
* Clock with multiple selectable parents. Implements .get_parent, .set_parent
|
|
|
|
* and .recalc_rate
|
|
|
|
*
|
|
|
|
* Flags:
|
|
|
|
* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
|
2012-04-17 05:15:35 -06:00
|
|
|
* CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
|
2013-06-08 08:47:17 -06:00
|
|
|
* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
|
|
|
|
* register, and mask of mux bits are in higher 16-bit of this register.
|
|
|
|
* While setting the mux bits, higher 16-bit should also be updated to
|
|
|
|
* indicate changing mux bits.
|
2012-03-16 00:11:20 -06:00
|
|
|
*/
|
|
|
|
struct clk_mux {
|
|
|
|
struct clk_hw hw;
|
|
|
|
void __iomem *reg;
|
2013-03-22 06:07:53 -06:00
|
|
|
u32 *table;
|
|
|
|
u32 mask;
|
2012-03-16 00:11:20 -06:00
|
|
|
u8 shift;
|
|
|
|
u8 flags;
|
|
|
|
spinlock_t *lock;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define CLK_MUX_INDEX_ONE BIT(0)
|
|
|
|
#define CLK_MUX_INDEX_BIT BIT(1)
|
2013-06-08 08:47:17 -06:00
|
|
|
#define CLK_MUX_HIWORD_MASK BIT(2)
|
2013-07-22 17:49:18 -06:00
|
|
|
#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */
|
2012-03-16 00:11:20 -06:00
|
|
|
|
2012-03-27 01:23:23 -06:00
|
|
|
extern const struct clk_ops clk_mux_ops;
|
2013-07-22 17:49:18 -06:00
|
|
|
extern const struct clk_ops clk_mux_ro_ops;
|
2013-03-22 06:07:53 -06:00
|
|
|
|
2012-03-16 00:11:20 -06:00
|
|
|
struct clk *clk_register_mux(struct device *dev, const char *name,
|
2012-03-21 14:01:20 -06:00
|
|
|
const char **parent_names, u8 num_parents, unsigned long flags,
|
2012-03-16 00:11:20 -06:00
|
|
|
void __iomem *reg, u8 shift, u8 width,
|
|
|
|
u8 clk_mux_flags, spinlock_t *lock);
|
2012-03-16 00:11:19 -06:00
|
|
|
|
2013-03-22 06:07:53 -06:00
|
|
|
struct clk *clk_register_mux_table(struct device *dev, const char *name,
|
|
|
|
const char **parent_names, u8 num_parents, unsigned long flags,
|
|
|
|
void __iomem *reg, u8 shift, u32 mask,
|
|
|
|
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
|
|
|
|
|
2013-04-12 05:57:44 -06:00
|
|
|
void of_fixed_factor_clk_setup(struct device_node *node);
|
|
|
|
|
2012-05-03 04:06:14 -06:00
|
|
|
/**
|
|
|
|
* struct clk_fixed_factor - fixed multiplier and divider clock
|
|
|
|
*
|
|
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
|
|
* @mult: multiplier
|
|
|
|
* @div: divider
|
|
|
|
*
|
|
|
|
* Clock with a fixed multiplier and divider. The output frequency is the
|
|
|
|
* parent clock rate divided by div and multiplied by mult.
|
|
|
|
* Implements .recalc_rate, .set_rate and .round_rate
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct clk_fixed_factor {
|
|
|
|
struct clk_hw hw;
|
|
|
|
unsigned int mult;
|
|
|
|
unsigned int div;
|
|
|
|
};
|
|
|
|
|
|
|
|
extern struct clk_ops clk_fixed_factor_ops;
|
|
|
|
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
|
|
|
|
const char *parent_name, unsigned long flags,
|
|
|
|
unsigned int mult, unsigned int div);
|
|
|
|
|
2013-03-20 06:00:34 -06:00
|
|
|
/***
|
|
|
|
* struct clk_composite - aggregate clock of mux, divider and gate clocks
|
|
|
|
*
|
|
|
|
* @hw: handle between common and hardware-specific interfaces
|
2013-04-11 12:31:36 -06:00
|
|
|
* @mux_hw: handle between composite and hardware-specific mux clock
|
|
|
|
* @rate_hw: handle between composite and hardware-specific rate clock
|
|
|
|
* @gate_hw: handle between composite and hardware-specific gate clock
|
2013-03-20 06:00:34 -06:00
|
|
|
* @mux_ops: clock ops for mux
|
2013-04-11 12:31:36 -06:00
|
|
|
* @rate_ops: clock ops for rate
|
2013-03-20 06:00:34 -06:00
|
|
|
* @gate_ops: clock ops for gate
|
|
|
|
*/
|
|
|
|
struct clk_composite {
|
|
|
|
struct clk_hw hw;
|
|
|
|
struct clk_ops ops;
|
|
|
|
|
|
|
|
struct clk_hw *mux_hw;
|
2013-04-11 12:31:36 -06:00
|
|
|
struct clk_hw *rate_hw;
|
2013-03-20 06:00:34 -06:00
|
|
|
struct clk_hw *gate_hw;
|
|
|
|
|
|
|
|
const struct clk_ops *mux_ops;
|
2013-04-11 12:31:36 -06:00
|
|
|
const struct clk_ops *rate_ops;
|
2013-03-20 06:00:34 -06:00
|
|
|
const struct clk_ops *gate_ops;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct clk *clk_register_composite(struct device *dev, const char *name,
|
|
|
|
const char **parent_names, int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
2013-04-11 12:31:36 -06:00
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
2013-03-20 06:00:34 -06:00
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags);
|
|
|
|
|
2012-03-16 00:11:19 -06:00
|
|
|
/**
|
|
|
|
* clk_register - allocate a new clock, register it and return an opaque cookie
|
|
|
|
* @dev: device that is registering this clock
|
|
|
|
* @hw: link to hardware-specific clock data
|
|
|
|
*
|
|
|
|
* clk_register is the primary interface for populating the clock tree with new
|
|
|
|
* clock nodes. It returns a pointer to the newly allocated struct clk which
|
|
|
|
* cannot be dereferenced by driver code but may be used in conjuction with the
|
2012-03-29 15:30:40 -06:00
|
|
|
* rest of the clock API. In the event of an error clk_register will return an
|
|
|
|
* error code; drivers must test for an error code after calling clk_register.
|
2012-03-16 00:11:19 -06:00
|
|
|
*/
|
2012-04-25 23:58:56 -06:00
|
|
|
struct clk *clk_register(struct device *dev, struct clk_hw *hw);
|
2012-09-24 14:38:04 -06:00
|
|
|
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
|
2012-03-16 00:11:19 -06:00
|
|
|
|
2012-04-18 02:07:12 -06:00
|
|
|
void clk_unregister(struct clk *clk);
|
2012-09-24 14:38:04 -06:00
|
|
|
void devm_clk_unregister(struct device *dev, struct clk *clk);
|
2012-04-18 02:07:12 -06:00
|
|
|
|
2012-03-16 00:11:19 -06:00
|
|
|
/* helper functions */
|
|
|
|
const char *__clk_get_name(struct clk *clk);
|
|
|
|
struct clk_hw *__clk_get_hw(struct clk *clk);
|
|
|
|
u8 __clk_get_num_parents(struct clk *clk);
|
|
|
|
struct clk *__clk_get_parent(struct clk *clk);
|
2013-07-29 05:24:58 -06:00
|
|
|
struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
|
2012-12-11 12:25:08 -07:00
|
|
|
unsigned int __clk_get_enable_count(struct clk *clk);
|
|
|
|
unsigned int __clk_get_prepare_count(struct clk *clk);
|
2012-03-16 00:11:19 -06:00
|
|
|
unsigned long __clk_get_rate(struct clk *clk);
|
2013-12-21 02:34:47 -07:00
|
|
|
unsigned long __clk_get_accuracy(struct clk *clk);
|
2012-03-16 00:11:19 -06:00
|
|
|
unsigned long __clk_get_flags(struct clk *clk);
|
2013-03-12 13:26:02 -06:00
|
|
|
bool __clk_is_prepared(struct clk *clk);
|
2012-10-04 00:38:55 -06:00
|
|
|
bool __clk_is_enabled(struct clk *clk);
|
2012-03-16 00:11:19 -06:00
|
|
|
struct clk *__clk_lookup(const char *name);
|
2013-07-29 05:25:02 -06:00
|
|
|
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *best_parent_rate,
|
|
|
|
struct clk **best_parent_p);
|
2012-03-16 00:11:19 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME clock api without lock protection
|
|
|
|
*/
|
|
|
|
int __clk_prepare(struct clk *clk);
|
|
|
|
void __clk_unprepare(struct clk *clk);
|
|
|
|
void __clk_reparent(struct clk *clk, struct clk *new_parent);
|
|
|
|
unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
|
|
|
|
|
2012-04-09 13:50:06 -06:00
|
|
|
struct of_device_id;
|
|
|
|
|
|
|
|
typedef void (*of_clk_init_cb_t)(struct device_node *);
|
|
|
|
|
2013-04-30 18:58:28 -06:00
|
|
|
struct clk_onecell_data {
|
|
|
|
struct clk **clks;
|
|
|
|
unsigned int clk_num;
|
|
|
|
};
|
|
|
|
|
2013-10-22 02:39:36 -06:00
|
|
|
extern struct of_device_id __clk_of_table;
|
|
|
|
|
2013-04-30 18:58:28 -06:00
|
|
|
#define CLK_OF_DECLARE(name, compat, fn) \
|
|
|
|
static const struct of_device_id __clk_of_table_##name \
|
|
|
|
__used __section(__clk_of_table) \
|
|
|
|
= { .compatible = compat, .data = fn };
|
|
|
|
|
|
|
|
#ifdef CONFIG_OF
|
2012-04-09 13:50:06 -06:00
|
|
|
int of_clk_add_provider(struct device_node *np,
|
|
|
|
struct clk *(*clk_src_get)(struct of_phandle_args *args,
|
|
|
|
void *data),
|
|
|
|
void *data);
|
|
|
|
void of_clk_del_provider(struct device_node *np);
|
|
|
|
struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
|
|
|
|
void *data);
|
2012-08-22 07:36:27 -06:00
|
|
|
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
|
2013-10-08 00:12:13 -06:00
|
|
|
int of_clk_get_parent_count(struct device_node *np);
|
2012-04-09 13:50:06 -06:00
|
|
|
const char *of_clk_get_parent_name(struct device_node *np, int index);
|
2013-01-04 00:00:52 -07:00
|
|
|
|
2012-04-09 13:50:06 -06:00
|
|
|
void of_clk_init(const struct of_device_id *matches);
|
|
|
|
|
2013-04-30 18:58:28 -06:00
|
|
|
#else /* !CONFIG_OF */
|
2013-01-04 00:00:52 -07:00
|
|
|
|
2013-04-30 18:58:28 -06:00
|
|
|
static inline int of_clk_add_provider(struct device_node *np,
|
|
|
|
struct clk *(*clk_src_get)(struct of_phandle_args *args,
|
|
|
|
void *data),
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#define of_clk_del_provider(np) \
|
|
|
|
{ while (0); }
|
|
|
|
static inline struct clk *of_clk_src_simple_get(
|
|
|
|
struct of_phandle_args *clkspec, void *data)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-ENOENT);
|
|
|
|
}
|
|
|
|
static inline struct clk *of_clk_src_onecell_get(
|
|
|
|
struct of_phandle_args *clkspec, void *data)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-ENOENT);
|
|
|
|
}
|
|
|
|
static inline const char *of_clk_get_parent_name(struct device_node *np,
|
|
|
|
int index)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
#define of_clk_init(matches) \
|
|
|
|
{ while (0); }
|
|
|
|
#endif /* CONFIG_OF */
|
2013-07-22 06:14:40 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* wrap access to peripherals in accessor routines
|
|
|
|
* for improved portability across platforms
|
|
|
|
*/
|
|
|
|
|
clk: mpc512x: introduce COMMON_CLK for MPC512x (disabled)
this change implements a clock driver for the MPC512x PowerPC platform
which follows the COMMON_CLK approach and uses common clock drivers
shared with other platforms
this driver implements the publicly announced set of clocks (those
listed in the dt-bindings header file), as well as generates additional
'struct clk' items where the SoC hardware cannot easily get mapped to
the common primitives (shared code) of the clock API, or requires
"intermediate clock nodes" to represent clocks that have both gates and
dividers
the previous PPC_CLOCK implementation is kept in place and remains
active for the moment, the newly introduced CCF clock driver will
receive additional support for backwards compatibility in a subsequent
patch before it gets enabled and will replace the PPC_CLOCK approach
some of the clock items get pre-enabled in the clock driver to not have
them automatically disabled by the underlying clock subsystem because of
their being unused -- this approach is desirable because
- some of the clocks are useful to have for diagnostics and information
despite their not getting claimed by any drivers (CPU, internal and
external RAM, internal busses, boot media)
- some of the clocks aren't claimed by their peripheral drivers yet,
either because of missing driver support or because device tree specs
aren't available yet (but the workarounds will get removed as the
drivers get adjusted and the device tree provides the clock specs)
clkdev registration provides "alias names" for few clock items
- to not break those peripheral drivers which encode their component
index into the name that is used for clock lookup (UART, SPI, USB)
- to not break those drivers which use names for the clock lookup which
were encoded in the previous PPC_CLOCK implementation (NFC, VIU, CAN)
this workaround will get removed as these drivers get adjusted after
device tree based clock lookup has become available
the COMMON_CLK implementation copes with device trees which lack an
oscillator node (backwards compat), the REF clock is then derived from
the IPS bus frequency and multiplier values fetched from hardware
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-11-30 15:51:24 -07:00
|
|
|
#if IS_ENABLED(CONFIG_PPC)
|
|
|
|
|
|
|
|
static inline u32 clk_readl(u32 __iomem *reg)
|
|
|
|
{
|
|
|
|
return ioread32be(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void clk_writel(u32 val, u32 __iomem *reg)
|
|
|
|
{
|
|
|
|
iowrite32be(val, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* platform dependent I/O accessors */
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2013-07-22 06:14:40 -06:00
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static inline u32 clk_readl(u32 __iomem *reg)
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{
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return readl(reg);
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}
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static inline void clk_writel(u32 val, u32 __iomem *reg)
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{
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writel(val, reg);
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}
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clk: mpc512x: introduce COMMON_CLK for MPC512x (disabled)
this change implements a clock driver for the MPC512x PowerPC platform
which follows the COMMON_CLK approach and uses common clock drivers
shared with other platforms
this driver implements the publicly announced set of clocks (those
listed in the dt-bindings header file), as well as generates additional
'struct clk' items where the SoC hardware cannot easily get mapped to
the common primitives (shared code) of the clock API, or requires
"intermediate clock nodes" to represent clocks that have both gates and
dividers
the previous PPC_CLOCK implementation is kept in place and remains
active for the moment, the newly introduced CCF clock driver will
receive additional support for backwards compatibility in a subsequent
patch before it gets enabled and will replace the PPC_CLOCK approach
some of the clock items get pre-enabled in the clock driver to not have
them automatically disabled by the underlying clock subsystem because of
their being unused -- this approach is desirable because
- some of the clocks are useful to have for diagnostics and information
despite their not getting claimed by any drivers (CPU, internal and
external RAM, internal busses, boot media)
- some of the clocks aren't claimed by their peripheral drivers yet,
either because of missing driver support or because device tree specs
aren't available yet (but the workarounds will get removed as the
drivers get adjusted and the device tree provides the clock specs)
clkdev registration provides "alias names" for few clock items
- to not break those peripheral drivers which encode their component
index into the name that is used for clock lookup (UART, SPI, USB)
- to not break those drivers which use names for the clock lookup which
were encoded in the previous PPC_CLOCK implementation (NFC, VIU, CAN)
this workaround will get removed as these drivers get adjusted after
device tree based clock lookup has become available
the COMMON_CLK implementation copes with device trees which lack an
oscillator node (backwards compat), the REF clock is then derived from
the IPS bus frequency and multiplier values fetched from hardware
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-11-30 15:51:24 -07:00
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#endif /* platform dependent I/O accessors */
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2012-03-16 00:11:19 -06:00
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#endif /* CONFIG_COMMON_CLK */
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#endif /* CLK_PROVIDER_H */
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