Merge tag 'drm-intel-fixes-2014-11-07' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Black screen, screen corruption, hardware state corruption fixes. * tag 'drm-intel-fixes-2014-11-07' of git://anongit.freedesktop.org/drm-intel: drm/i915: safeguard against too high minimum brightness drm/i915: vlv: fix gunit HW state corruption during S4 suspend drm/i915: Disable caches for Global GTT.
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commit
03dca70852
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@ -986,6 +986,15 @@ static int i915_pm_freeze(struct device *dev)
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return i915_drm_freeze(drm_dev);
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}
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static int i915_pm_freeze_late(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct drm_device *drm_dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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return intel_suspend_complete(dev_priv);
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}
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static int i915_pm_thaw_early(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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@ -1570,6 +1579,7 @@ static const struct dev_pm_ops i915_pm_ops = {
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.resume_early = i915_pm_resume_early,
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.resume = i915_pm_resume,
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.freeze = i915_pm_freeze,
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.freeze_late = i915_pm_freeze_late,
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.thaw_early = i915_pm_thaw_early,
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.thaw = i915_pm_thaw,
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.poweroff = i915_pm_poweroff,
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@ -1902,6 +1902,22 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
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GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
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GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
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if (!USES_PPGTT(dev_priv->dev))
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/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
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* so RTL will always use the value corresponding to
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* pat_sel = 000".
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* So let's disable cache for GGTT to avoid screen corruptions.
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* MOCS still can be used though.
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* - System agent ggtt writes (i.e. cpu gtt mmaps) already work
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* before this patch, i.e. the same uncached + snooping access
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* like on gen6/7 seems to be in effect.
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* - So this just fixes blitter/render access. Again it looks
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* like it's not just uncached access, but uncached + snooping.
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* So we can still hold onto all our assumptions wrt cpu
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* clflushing on LLC machines.
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*/
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pat = GEN8_PPAT(0, GEN8_PPAT_UC);
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/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
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* write would work. */
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I915_WRITE(GEN8_PRIVATE_PAT, pat);
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@ -1098,12 +1098,25 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector)
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struct drm_device *dev = connector->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_panel *panel = &connector->panel;
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int min;
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WARN_ON(panel->backlight.max == 0);
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/*
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* XXX: If the vbt value is 255, it makes min equal to max, which leads
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* to problems. There are such machines out there. Either our
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* interpretation is wrong or the vbt has bogus data. Or both. Safeguard
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* against this by letting the minimum be at most (arbitrarily chosen)
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* 25% of the max.
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*/
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min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
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if (min != dev_priv->vbt.backlight.min_brightness) {
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DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
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dev_priv->vbt.backlight.min_brightness, min);
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}
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/* vbt value is a coefficient in range [0..255] */
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return scale(dev_priv->vbt.backlight.min_brightness, 0, 255,
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0, panel->backlight.max);
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return scale(min, 0, 255, 0, panel->backlight.max);
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}
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static int bdw_setup_backlight(struct intel_connector *connector)
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