[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -778,6 +778,18 @@ config ARM_ERRATA_458693
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in the ACTLR register. Note that setting specific bits in the ACTLR
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register may not be available in non-secure mode.
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config ARM_ERRATA_460075
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bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
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depends on CPU_V7
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help
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This option enables the workaround for the 460075 Cortex-A8 (r2p0)
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erratum. Any asynchronous access to the L2 cache may encounter a
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situation in which recent store transactions to the L2 cache are lost
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and overwritten with stale memory contents from external memory. The
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workaround disables the write-allocate mode for the L2 cache via the
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ACTLR register. Note that setting specific bits in the ACTLR register
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may not be available in non-secure mode.
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endmenu
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source "arch/arm/common/Kconfig"
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@ -193,6 +193,11 @@ __v7_setup:
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orr r10, r10, #(1 << 5) @ set L1NEON to 1
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orr r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcr p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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mov r10, #0
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#ifdef HARVARD_CACHE
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