drm/radeon: use gart for DMA IB tests
Use gart rather than vram to avoid having to deal with
the HDP cache.
Port of adfed2b058
(drm/radeon: use gart memory for DMA ring tests)
to the IB tests.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
parent
8efe82ca90
commit
0b021c5802
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@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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gpu_addr = rdev->wb.gpu_addr + index;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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rdev->wb.wb[index/4] = cpu_to_le32(tmp);
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr);
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ib.ptr[3] = 1;
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ib.ptr[4] = 0xDEADBEEF;
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ib.length_dw = 5;
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@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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gpu_addr = rdev->wb.gpu_addr + index;
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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@ -357,8 +357,8 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
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ib.ptr[3] = 0xDEADBEEF;
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ib.length_dw = 4;
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@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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