drm/etnaviv: handle MMU exception in IRQ handler
Bit 30 of the interrupt status signals an MMU exception. Handle this condition properly and dump some useful registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -1363,6 +1363,21 @@ static irqreturn_t irq_handler(int irq, void *data)
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intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
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}
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if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
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int i;
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dev_err_ratelimited(gpu->dev,
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"MMU fault status 0x%08x\n",
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gpu_read(gpu, VIVS_MMUv2_STATUS));
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for (i = 0; i < 4; i++) {
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dev_err_ratelimited(gpu->dev,
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"MMU %d fault addr 0x%08x\n",
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i, gpu_read(gpu,
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VIVS_MMUv2_EXCEPTION_ADDR(i)));
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}
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intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
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}
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while ((event = ffs(intr)) != 0) {
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struct fence *fence;
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@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53)
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- common.xml ( 18437 bytes, from 2015-12-12 09:02:53)
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- state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37)
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- common.xml ( 20583 bytes, from 2016-06-07 05:22:38)
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Copyright (C) 2015
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Copyright (C) 2016
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*/
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@ -78,9 +78,10 @@ Copyright (C) 2015
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#define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200
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#define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010
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#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff
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#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff
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#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0
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#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)
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#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000
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#define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000
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#define VIVS_HI_INTR_ENBL 0x00000014
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