ARM: OMAP5: Add the WakeupGen IP updates
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -11,15 +11,20 @@
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#ifndef OMAP_ARCH_WAKEUPGEN_H
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#define OMAP_ARCH_WAKEUPGEN_H
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/* OMAP4 and OMAP5 has same base address */
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#define OMAP_WKUPGEN_BASE 0x48281000
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#define OMAP_WKG_CONTROL_0 0x00
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#define OMAP_WKG_ENB_A_0 0x10
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#define OMAP_WKG_ENB_B_0 0x14
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#define OMAP_WKG_ENB_C_0 0x18
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#define OMAP_WKG_ENB_D_0 0x1c
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#define OMAP_WKG_ENB_E_0 0x20
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#define OMAP_WKG_ENB_A_1 0x410
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#define OMAP_WKG_ENB_B_1 0x414
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#define OMAP_WKG_ENB_C_1 0x418
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#define OMAP_WKG_ENB_D_1 0x41c
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#define OMAP_WKG_ENB_E_1 0x420
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#define OMAP_AUX_CORE_BOOT_0 0x800
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#define OMAP_AUX_CORE_BOOT_1 0x804
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#define OMAP_PTMSYNCREQ_MASK 0xc00
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@ -28,4 +33,6 @@
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#define OMAP_TIMESTAMPCYCLEHI 0xc0c
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extern int __init omap_wakeupgen_init(void);
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extern void __iomem *omap_get_wakeupgen_base(void);
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extern int omap_secure_apis_support(void);
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#endif
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@ -17,8 +17,10 @@
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/omap-wakeupgen.h>
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#include "common.h"
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@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
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*/
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void __ref platform_cpu_die(unsigned int cpu)
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{
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unsigned int this_cpu;
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unsigned int boot_cpu = 0;
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void __iomem *base = omap_get_wakeupgen_base();
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flush_cache_all();
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dsb();
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@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
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/*
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* we're ready for shutdown now, so do it
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*/
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if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
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pr_err("Secure clear status failed\n");
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if (omap_secure_apis_support()) {
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if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
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pr_err("Secure clear status failed\n");
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} else {
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__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
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}
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for (;;) {
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/*
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* Enter into low power state
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*/
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omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
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this_cpu = smp_processor_id();
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if (omap_read_auxcoreboot0() == this_cpu) {
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if (omap_secure_apis_support())
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boot_cpu = omap_read_auxcoreboot0();
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else
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boot_cpu =
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__raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
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if (boot_cpu == smp_processor_id()) {
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/*
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* OK, proper wakeup, we're done
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*/
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@ -26,6 +26,8 @@
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#include <mach/hardware.h>
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#include <mach/omap-secure.h>
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#include <mach/omap-wakeupgen.h>
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#include <asm/cputype.h>
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#include "iomap.h"
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#include "common.h"
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@ -73,6 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static struct clockdomain *cpu1_clkdm;
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static bool booted;
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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if (omap_secure_apis_support())
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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else
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__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
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flush_cache_all();
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smp_wmb();
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@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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static void __init wakeup_secondary(void)
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{
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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* Write the address of secondary startup routine into the
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* AuxCoreBoot1 where ROM code will jump and start executing
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* on secondary core once out of WFE
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
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if (omap_secure_apis_support())
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omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
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else
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__raw_writel(virt_to_phys(omap5_secondary_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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smp_wmb();
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/*
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@ -33,18 +33,23 @@
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#include "omap4-sar-layout.h"
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#include "common.h"
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#define NR_REG_BANKS 4
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#define MAX_IRQS 128
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#define MAX_NR_REG_BANKS 5
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#define MAX_IRQS 160
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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#define CPU0_ID 0x0
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#define CPU1_ID 0x1
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#define OMAP4_NR_BANKS 4
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#define OMAP4_NR_IRQS 128
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[NR_IRQS];
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static unsigned int irq_banks = MAX_NR_REG_BANKS;
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static unsigned int max_irqs = MAX_IRQS;
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static unsigned int omap_secure_apis;
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/*
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* Static helper functions.
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@ -146,13 +151,13 @@ static void wakeupgen_unmask(struct irq_data *d)
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
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static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
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static void _wakeupgen_save_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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for (i = 0; i < irq_banks; i++)
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per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
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}
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@ -160,7 +165,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
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}
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@ -168,7 +173,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
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{
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u8 i;
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for (i = 0; i < NR_REG_BANKS; i++)
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(reg, i, cpu);
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}
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@ -196,25 +201,14 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
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#endif
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#ifdef CONFIG_CPU_PM
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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static inline void omap4_irq_save_context(void)
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{
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u32 i, val;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return;
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if (!sar_base)
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sar_base = omap4_get_sar_ram_base();
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for (i = 0; i < NR_REG_BANKS; i++) {
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 127 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
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val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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static inline void omap5_irq_save_context(void)
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{
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u32 i, val;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 159 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
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/* Set the Backup Bit Mask status */
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val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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}
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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{
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if (!sar_base)
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sar_base = omap4_get_sar_ram_base();
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if (soc_is_omap54xx())
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omap5_irq_save_context();
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else
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omap4_irq_save_context();
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}
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/*
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static void irq_sar_clear(void)
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{
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u32 val;
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val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
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u32 offset = SAR_BACKUP_STATUS_OFFSET;
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if (soc_is_omap54xx())
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offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
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val = __raw_readl(sar_base + offset);
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val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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__raw_writel(val, sar_base + offset);
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}
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/*
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static void __init irq_pm_init(void)
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{
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cpu_pm_register_notifier(&irq_notifier_block);
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/* FIXME: Remove this when MPU OSWR support is added */
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if (!soc_is_omap54xx())
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cpu_pm_register_notifier(&irq_notifier_block);
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}
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#else
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static void __init irq_pm_init(void)
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{}
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#endif
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void __iomem *omap_get_wakeupgen_base(void)
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{
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return wakeupgen_base;
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}
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int omap_secure_apis_support(void)
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{
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return omap_secure_apis;
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}
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/*
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* Initialise the wakeupgen module.
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*/
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@ -358,12 +416,18 @@ int __init omap_wakeupgen_init(void)
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}
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/* Static mapping, never released */
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wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
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wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
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if (WARN_ON(!wakeupgen_base))
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return -ENOMEM;
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if (cpu_is_omap44xx()) {
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irq_banks = OMAP4_NR_BANKS;
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max_irqs = OMAP4_NR_IRQS;
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omap_secure_apis = 1;
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}
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/* Clear all IRQ bitmasks at wakeupGen level */
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for (i = 0; i < NR_REG_BANKS; i++) {
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for (i = 0; i < irq_banks; i++) {
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wakeupgen_writel(0, i, CPU0_ID);
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wakeupgen_writel(0, i, CPU1_ID);
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}
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*/
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/* Associate all the IRQs to boot CPU like GIC init does. */
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for (i = 0; i < NR_IRQS; i++)
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for (i = 0; i < max_irqs; i++)
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irq_target_cpu[i] = boot_cpu;
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irq_hotplug_init();
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@ -12,7 +12,7 @@
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#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
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/*
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* SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
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* SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
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*/
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#define SAR_BANK1_OFFSET 0x0000
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#define SAR_BANK2_OFFSET 0x1000
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#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
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#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
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/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
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#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
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#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
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#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
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#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
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#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
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#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
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#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
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#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
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#endif
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