MLK-20222-2 ARM64:dts: Update SCFW API
Update SCFW API to the following commit: " ("430d1e3646fbe75e339e18abf2330565eac906e0") Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Fri Nov 2 15:25:45 2018 -0500 SCF-105: RN updates. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>pull/10/head
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright 2017-2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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* Header file used to configure SoC pad list.
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*/
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#ifndef _SC_PADS_H
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#define _SC_PADS_H
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#ifndef SC_PADS_H
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#define SC_PADS_H
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/* Includes */
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/* Defines */
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#define SC_P_ALL UINT16_MAX /* All pads */
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/*!
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* @name Pad Definitions
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*/
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@ -973,6 +971,7 @@
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#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3
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#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
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#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
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/*@}*/
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#endif /* _SC_PADS_H */
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#endif /* SC_PADS_H */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright 2017-2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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* Header file used to configure SoC pad list.
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*/
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#ifndef _SC_PADS_H
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#define _SC_PADS_H
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#ifndef SC_PADS_H
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#define SC_PADS_H
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/* Includes */
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/* Defines */
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#define SC_P_ALL UINT16_MAX /* All pads */
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/*!
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* @name Pad Definitions
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*/
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@ -771,4 +769,4 @@
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#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
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/*@}*/
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#endif /* _SC_PADS_H */
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#endif /* SC_PADS_H */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright 2017-2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RSCRC_IMX_H
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#define __DT_BINDINGS_RSCRC_IMX_H
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#ifndef DT_BINDINGS_RSCRC_IMX_H
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#define DT_BINDINGS_RSCRC_IMX_H
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/*!
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* These defines are used to indicate a resource. Resources include peripherals
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#define SC_R_IRQSTR_SCU2 321
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#define SC_R_IRQSTR_DSP 322
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#define SC_R_ELCDIF_PLL 323
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#define SC_R_UNUSED6 324
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#define SC_R_OCRAM 324
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#define SC_R_AUDIO_PLL_0 325
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#define SC_R_PI_0 326
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#define SC_R_PI_0_PWM_0 327
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#define SC_R_VPU_MU_3 538
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#define SC_R_VPU_ENC_1 539
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#define SC_R_VPU 540
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#define SC_R_LAST 541
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#define SC_R_DMA_5_CH0 541
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#define SC_R_DMA_5_CH1 542
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#define SC_R_DMA_5_CH2 543
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#define SC_R_DMA_5_CH3 544
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#define SC_R_ATTESTATION 545
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#define SC_R_PERF 546
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#define SC_R_LAST 547
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#endif /* __DT_BINDINGS_RSCRC_IMX_H */
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#endif /* DT_BINDINGS_RSCRC_IMX_H */
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