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MLK-20222-2 ARM64:dts: Update SCFW API 

Update SCFW API to the following commit:
    "
        ("430d1e3646fbe75e339e18abf2330565eac906e0")
        Author: Chuck Cannon <chuck.cannon@nxp.com>
        Date:   Fri Nov 2 15:25:45 2018 -0500

        SCF-105: RN updates.
    "

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
pull/10/head
Ranjani Vaidyanathan 2018-11-02 15:58:52 -05:00
parent 1c21a146dc
commit 2559ea1a96
3 changed files with 21 additions and 18 deletions
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11
include/dt-bindings/pinctrl/pads-imx8qm.h
View File

@ -1,6 +1,6 @@
/* /*
* Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP * Copyright 2017-2018 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -9,15 +9,13 @@
* Header file used to configure SoC pad list. * Header file used to configure SoC pad list.
*/ */
#ifndef _SC_PADS_H #ifndef SC_PADS_H
#define _SC_PADS_H #define SC_PADS_H
/* Includes */ /* Includes */
/* Defines */ /* Defines */
#define SC_P_ALL UINT16_MAX /* All pads */
/*! /*!
* @name Pad Definitions * @name Pad Definitions
*/ */
@ -973,6 +971,7 @@
#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
/*@}*/ /*@}*/
#endif /* _SC_PADS_H */ #endif /* SC_PADS_H */

10
include/dt-bindings/pinctrl/pads-imx8qxp.h
View File

@ -1,6 +1,6 @@
/* /*
* Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP * Copyright 2017-2018 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -9,15 +9,13 @@
* Header file used to configure SoC pad list. * Header file used to configure SoC pad list.
*/ */
#ifndef _SC_PADS_H #ifndef SC_PADS_H
#define _SC_PADS_H #define SC_PADS_H
/* Includes */ /* Includes */
/* Defines */ /* Defines */
#define SC_P_ALL UINT16_MAX /* All pads */
/*! /*!
* @name Pad Definitions * @name Pad Definitions
*/ */
@ -771,4 +769,4 @@
#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 #define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
/*@}*/ /*@}*/
#endif /* _SC_PADS_H */ #endif /* SC_PADS_H */

18
include/dt-bindings/soc/imx_rsrc.h
View File

@ -1,12 +1,12 @@
/* /*
* Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP * Copyright 2017-2018 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#ifndef __DT_BINDINGS_RSCRC_IMX_H #ifndef DT_BINDINGS_RSCRC_IMX_H
#define __DT_BINDINGS_RSCRC_IMX_H #define DT_BINDINGS_RSCRC_IMX_H
/*! /*!
* These defines are used to indicate a resource. Resources include peripherals * These defines are used to indicate a resource. Resources include peripherals
@ -337,7 +337,7 @@
#define SC_R_IRQSTR_SCU2 321 #define SC_R_IRQSTR_SCU2 321
#define SC_R_IRQSTR_DSP 322 #define SC_R_IRQSTR_DSP 322
#define SC_R_ELCDIF_PLL 323 #define SC_R_ELCDIF_PLL 323
#define SC_R_UNUSED6 324 #define SC_R_OCRAM 324
#define SC_R_AUDIO_PLL_0 325 #define SC_R_AUDIO_PLL_0 325
#define SC_R_PI_0 326 #define SC_R_PI_0 326
#define SC_R_PI_0_PWM_0 327 #define SC_R_PI_0_PWM_0 327
@ -554,6 +554,12 @@
#define SC_R_VPU_MU_3 538 #define SC_R_VPU_MU_3 538
#define SC_R_VPU_ENC_1 539 #define SC_R_VPU_ENC_1 539
#define SC_R_VPU 540 #define SC_R_VPU 540
#define SC_R_LAST 541 #define SC_R_DMA_5_CH0 541
#define SC_R_DMA_5_CH1 542
#define SC_R_DMA_5_CH2 543
#define SC_R_DMA_5_CH3 544
#define SC_R_ATTESTATION 545
#define SC_R_PERF 546
#define SC_R_LAST 547
#endif /* __DT_BINDINGS_RSCRC_IMX_H */ #endif /* DT_BINDINGS_RSCRC_IMX_H */