pinctrl: sh-pfc: Updates for v4.9 (take three)
- Return pinconf with arguments in packed format, - MSIOF and QSPI pin groups on R-Car V2H, - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX2P50AAoJEEgEtLw/Ve77rY4P/0/bg+WExjkEbUFuzj1BW/06 /oXjuGQbJv9MLMgfaCpQqvxhn8UKn3SAGmdD5lH6gedUpkDjokx2fWtOKQBhKma+ 9yY/8e9lWScvK++OYsY/bvLlTnB49R6DNfLWWkMhHx9TP6bcBPlvgTJscF8siwAG Da55rvshks8rKevFM6yNVClHUPLbuwj58jTruwm72ZSpxiDfuHx0ORy9WfvPKgnq mOq4T3o6iSR3fGSqJqsDIgw6I3KnUmQLZWxUQnS9KyCu+Vt3W7tykixYaf4tcf/9 PJC2tfzk7HxLeeV/t+2LVjwshiTfyLLJ36/c7hRh48E/YdpPQ6N0ZFRlEuRO3/nP B9emzugTy+/IhdlDHlfAiL9c/3IjMhrULNWUott/5BTBHNHp6jN+vbnH3e8GZLyq bxVZVJLuq+lmusnNwXG02fE59ba2y+G9tyGiY/J9CDLQVxxAfayINM0395FPXoAK RBn/fdVo1HbbXAFeEig4amMF3psC0as04cdLs77FxBYwAPyzl3W3dgU7fpCDkLFU Rbd+HUmqfi+g117FPGe/dbvM3C30uvpt6LE1YPGgJEVF9ILt22EBV1Fgf6C2SMrP b2dGSjT+puVS6VfiUbrJD6/znYc3az2b1lY8nsbz5GPnl0hc4qWky6CPxe7Q1yj1 mxiEnZfTDvh3hTK7ONg5 =APGj -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 (take three) - Return pinconf with arguments in packed format, - MSIOF and QSPI pin groups on R-Car V2H, - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.steinar/wifi_calib_4_9_kernel
Linus Walleij
commit
3049d1343f
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@ -13,6 +13,10 @@
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#include "sh_pfc.h"
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/*
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* Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
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* which case they support both 3.3V and 1.8V signalling.
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*/
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_26(1, fn, sfx), \
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@ -20,7 +24,15 @@
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PORT_GP_32(3, fn, sfx), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_32(5, fn, sfx), \
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PORT_GP_32(6, fn, sfx), \
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PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(6, 24, fn, sfx), \
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PORT_GP_1(6, 25, fn, sfx), \
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PORT_GP_1(6, 26, fn, sfx), \
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PORT_GP_1(6, 27, fn, sfx), \
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PORT_GP_1(6, 28, fn, sfx), \
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PORT_GP_1(6, 29, fn, sfx), \
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PORT_GP_1(6, 30, fn, sfx), \
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PORT_GP_1(6, 31, fn, sfx), \
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PORT_GP_26(7, fn, sfx)
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enum {
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@ -6404,9 +6416,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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{
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if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
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return -EINVAL;
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*pocctrl = 0xe606008c;
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return 31 - (pin & 0x1f);
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}
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static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
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.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
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};
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#ifdef CONFIG_PINCTRL_PFC_R8A7791
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const struct sh_pfc_soc_info r8a7791_pinmux_info = {
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.name = "r8a77910_pfc",
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.ops = &r8a7791_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@ -1034,6 +1034,87 @@ static const unsigned int lbsc_ex_cs5_pins[] = {
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static const unsigned int lbsc_ex_cs5_mux[] = {
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EX_CS5_N_MARK,
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};
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/* - MSIOF0 ----------------------------------------------------------------- */
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static const unsigned int msiof0_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(10, 0),
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};
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static const unsigned int msiof0_clk_mux[] = {
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MSIOF0_SCK_MARK,
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};
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static const unsigned int msiof0_sync_pins[] = {
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/* SYNC */
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RCAR_GP_PIN(10, 1),
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};
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static const unsigned int msiof0_sync_mux[] = {
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MSIOF0_SYNC_MARK,
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};
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static const unsigned int msiof0_rx_pins[] = {
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/* RXD */
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RCAR_GP_PIN(10, 4),
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};
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static const unsigned int msiof0_rx_mux[] = {
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MSIOF0_RXD_MARK,
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};
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static const unsigned int msiof0_tx_pins[] = {
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/* TXD */
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RCAR_GP_PIN(10, 3),
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};
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static const unsigned int msiof0_tx_mux[] = {
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MSIOF0_TXD_MARK,
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};
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/* - MSIOF1 ----------------------------------------------------------------- */
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static const unsigned int msiof1_clk_pins[] = {
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/* SCK */
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RCAR_GP_PIN(10, 5),
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};
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static const unsigned int msiof1_clk_mux[] = {
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MSIOF1_SCK_MARK,
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};
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static const unsigned int msiof1_sync_pins[] = {
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/* SYNC */
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RCAR_GP_PIN(10, 6),
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};
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static const unsigned int msiof1_sync_mux[] = {
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MSIOF1_SYNC_MARK,
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};
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static const unsigned int msiof1_rx_pins[] = {
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/* RXD */
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RCAR_GP_PIN(10, 9),
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};
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static const unsigned int msiof1_rx_mux[] = {
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MSIOF1_RXD_MARK,
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};
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static const unsigned int msiof1_tx_pins[] = {
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/* TXD */
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RCAR_GP_PIN(10, 8),
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};
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static const unsigned int msiof1_tx_mux[] = {
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MSIOF1_TXD_MARK,
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};
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/* - QSPI ------------------------------------------------------------------- */
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static const unsigned int qspi_ctrl_pins[] = {
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/* SPCLK, SSL */
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RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
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};
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static const unsigned int qspi_ctrl_mux[] = {
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SPCLK_MARK, SSL_MARK,
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};
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static const unsigned int qspi_data2_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
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};
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static const unsigned int qspi_data2_mux[] = {
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MOSI_IO0_MARK, MISO_IO1_MARK,
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};
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static const unsigned int qspi_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
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RCAR_GP_PIN(3, 24),
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};
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static const unsigned int qspi_data4_mux[] = {
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MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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@ -1585,6 +1666,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(lbsc_ex_cs3),
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SH_PFC_PIN_GROUP(lbsc_ex_cs4),
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SH_PFC_PIN_GROUP(lbsc_ex_cs5),
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SH_PFC_PIN_GROUP(msiof0_clk),
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SH_PFC_PIN_GROUP(msiof0_sync),
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SH_PFC_PIN_GROUP(msiof0_rx),
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SH_PFC_PIN_GROUP(msiof0_tx),
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SH_PFC_PIN_GROUP(msiof1_clk),
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SH_PFC_PIN_GROUP(msiof1_sync),
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SH_PFC_PIN_GROUP(msiof1_rx),
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SH_PFC_PIN_GROUP(msiof1_tx),
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SH_PFC_PIN_GROUP(qspi_ctrl),
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SH_PFC_PIN_GROUP(qspi_data2),
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SH_PFC_PIN_GROUP(qspi_data4),
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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@ -1708,6 +1800,26 @@ static const char * const lbsc_groups[] = {
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"lbsc_ex_cs5",
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};
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static const char * const msiof0_groups[] = {
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"msiof0_clk",
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"msiof0_sync",
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"msiof0_rx",
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"msiof0_tx",
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};
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static const char * const msiof1_groups[] = {
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"msiof1_clk",
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"msiof1_sync",
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"msiof1_rx",
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"msiof1_tx",
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};
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static const char * const qspi_groups[] = {
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"qspi_ctrl",
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"qspi_data2",
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"qspi_data4",
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};
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static const char * const scif0_groups[] = {
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"scif0_data",
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"scif0_clk",
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@ -1808,6 +1920,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(du1),
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SH_PFC_FUNCTION(intc),
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SH_PFC_FUNCTION(lbsc),
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SH_PFC_FUNCTION(msiof0),
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SH_PFC_FUNCTION(msiof1),
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SH_PFC_FUNCTION(qspi),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif3),
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SH_PFC_FUNCTION(sdhi0),
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@ -22,7 +22,9 @@
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PORT_GP_32(3, fn, sfx), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_28(5, fn, sfx), \
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PORT_GP_26(6, fn, sfx)
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PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(6, 24, fn, sfx), \
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PORT_GP_1(6, 25, fn, sfx)
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enum {
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PINMUX_RESERVED = 0,
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@ -5160,8 +5162,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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{
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*pocctrl = 0xe606006c;
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switch (pin & 0x1f) {
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case 6: return 23;
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case 7: return 16;
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case 14: return 15;
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case 15: return 8;
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case 0 ... 5:
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case 8 ... 13:
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return 22 - (pin & 0x1f);
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case 16 ... 23:
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return 47 - (pin & 0x1f);
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}
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return -EINVAL;
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}
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static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
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.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
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};
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const struct sh_pfc_soc_info r8a7794_pinmux_info = {
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.name = "r8a77940_pfc",
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.ops = &r8a7794_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@ -23,8 +23,12 @@
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PORT_GP_16(0, fn, sfx), \
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PORT_GP_29(1, fn, sfx), \
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PORT_GP_15(2, fn, sfx), \
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PORT_GP_16(3, fn, sfx), \
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PORT_GP_18(4, fn, sfx), \
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PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(3, 12, fn, sfx), \
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PORT_GP_1(3, 13, fn, sfx), \
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PORT_GP_1(3, 14, fn, sfx), \
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PORT_GP_1(3, 15, fn, sfx), \
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PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_26(5, fn, sfx), \
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PORT_GP_32(6, fn, sfx), \
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PORT_GP_4(7, fn, sfx)
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@ -2627,8 +2631,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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{
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int bit = -EINVAL;
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*pocctrl = 0xe6060380;
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if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
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bit = pin & 0x1f;
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if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
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bit = (pin & 0x1f) + 12;
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return bit;
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}
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static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
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.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
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};
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const struct sh_pfc_soc_info r8a7796_pinmux_info = {
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.name = "r8a77960_pfc",
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.ops = &r8a7796_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@ -596,6 +596,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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struct sh_pfc *pfc = pmx->pfc;
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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unsigned int arg;
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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@ -616,7 +617,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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if (bias != param)
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return -EINVAL;
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*config = 0;
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arg = 0;
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break;
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}
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@ -627,7 +628,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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if (ret < 0)
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return ret;
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*config = ret;
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arg = ret;
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break;
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}
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@ -646,7 +647,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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val = sh_pfc_read_reg(pfc, pocctrl, 32);
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spin_unlock_irqrestore(&pfc->lock, flags);
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*config = (val & BIT(bit)) ? 3300 : 1800;
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arg = (val & BIT(bit)) ? 3300 : 1800;
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break;
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}
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@ -654,6 +655,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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@ -422,9 +422,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
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PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
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#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
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#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
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#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
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PORT_GP_CFG_23(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
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#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
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#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
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PORT_GP_CFG_24(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
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#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
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|
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Loading…
Reference in New Issue