Merge branches 'pci/host-designware', 'pci/host-dra7xx', 'pci/host-exynos', 'pci/host-generic', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-spear' and 'pci/host-tegra' into next
* pci/host-designware: PCI: designware: Add a blank line after declarations * pci/host-dra7xx: PCI: dra7xx: Add __init annotation to dra7xx_add_pcie_port() PCI: dra7xx: Rename add_pcie_port() to dra7xx_add_pcie_port() * pci/host-exynos: PCI: exynos: Remove unnecessary return statement PCI: exynos: Add exynos prefix to add_pcie_port()/pcie_init() * pci/host-generic: PCI: generic: Convert to DT resource parsing API PCI: generic: Allocate config space windows after limiting bus number range * pci/host-imx6: PCI: imx6: Use tabs for indentation * pci/host-keystone: PCI: keystone: Remove unnecessary OOM message PCI: keystone: Make ks_dw_pcie_msi_domain_ops static * pci/host-layerscape: PCI: layerscape: Add Freescale Layerscape PCIe driver * pci/host-mvebu: PCI: mvebu: Add a blank line after declarations * pci/host-rcar: PCI: rcar: Make rcar_pci static * pci/host-spear: PCI: spear: Remove unnecessary OOM message PCI: spear: Add __init annotation to spear13xx_add_pcie_port() PCI: spear: Rename add_pcie_port(), pcie_init() to spear13xx_add_pcie_port(), etc. * pci/host-tegra: PCI: tegra: Add Kconfig help text PCI: tegra: Do not build on 64-bit ARMwifi-calibration
Bjorn Helgaas
parent
f114040e3e
2c992f3779
e73044a069
bc512c5a8c
dbf9826d57
d88a7ef99e
6670070742
62d0ff83c6
cf3a9d6bae
3c70637f75
20f9ece101
6b1c4d7674
commit
35437e3d9b
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@ -0,0 +1,42 @@
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Freescale Layerscape PCIe controller
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
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- reg: base addresses and lengths of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The interrupt that is asserted for controller interrupts
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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This is used to get SCFG PEXN registers
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Example:
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pcie@3400000 {
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compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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};
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10
MAINTAINERS
10
MAINTAINERS
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@ -6983,6 +6983,16 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci.txt
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F: drivers/pci/host/pci-xgene.c
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PCI DRIVER FOR FREESCALE LAYERSCAPE
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M: Minghuan Lian <minghuan.Lian@freescale.com>
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M: Mingkai Hu <mingkai.hu@freescale.com>
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M: Roy Zang <tie-fei.zang@freescale.com>
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L: linuxppc-dev@lists.ozlabs.org
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: drivers/pci/host/*layerscape*
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PCI DRIVER FOR IMX6
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M: Richard Zhu <r65037@freescale.com>
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M: Lucas Stach <l.stach@pengutronix.de>
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@ -32,7 +32,10 @@ config PCI_IMX6
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config PCI_TEGRA
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bool "NVIDIA Tegra PCIe controller"
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depends on ARCH_TEGRA
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depends on ARCH_TEGRA && !ARM64
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help
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Say Y here if you want support for the PCIe host controller found
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on NVIDIA Tegra SoCs.
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config PCI_RCAR_GEN2
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bool "Renesas R-Car Gen2 Internal PCI controller"
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@ -91,4 +94,12 @@ config PCI_XGENE
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There are 5 internal PCIe ports available. Each port is GEN3 capable
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and have varied lanes from x1 to x8.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller"
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depends on OF && ARM
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select PCIE_DW
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select MFD_SYSCON
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help
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Say Y here if you want PCIe controller support on Layerscape SoCs.
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endmenu
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@ -11,3 +11,4 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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@ -270,8 +270,8 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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return IRQ_HANDLED;
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}
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static int add_pcie_port(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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{
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int ret;
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struct pcie_port *pp;
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@ -398,7 +398,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dra7xx);
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ret = add_pcie_port(dra7xx, pdev);
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ret = dra7xx_add_pcie_port(dra7xx, pdev);
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if (ret < 0)
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goto err_add_port;
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@ -312,7 +312,6 @@ static void exynos_pcie_assert_reset(struct pcie_port *pp)
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if (exynos_pcie->reset_gpio >= 0)
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devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
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GPIOF_OUT_INIT_HIGH, "RESET");
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return;
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}
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static int exynos_pcie_establish_link(struct pcie_port *pp)
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@ -388,7 +387,6 @@ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
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val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
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exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
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return;
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}
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static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
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@ -400,7 +398,6 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
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val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
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IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
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exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
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return;
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}
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static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
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@ -429,7 +426,6 @@ static void exynos_pcie_msi_init(struct pcie_port *pp)
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val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
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val |= IRQ_MSI_ENABLE;
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exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
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return;
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}
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static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
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@ -438,8 +434,6 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
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if (IS_ENABLED(CONFIG_PCI_MSI))
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exynos_pcie_msi_init(pp);
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return;
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}
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static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
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@ -448,7 +442,6 @@ static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
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exynos_pcie_sideband_dbi_r_mode(pp, true);
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*val = readl(dbi_base);
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exynos_pcie_sideband_dbi_r_mode(pp, false);
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return;
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}
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static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
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@ -457,7 +450,6 @@ static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
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exynos_pcie_sideband_dbi_w_mode(pp, true);
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writel(val, dbi_base);
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exynos_pcie_sideband_dbi_w_mode(pp, false);
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return;
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}
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static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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@ -509,8 +501,8 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
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.host_init = exynos_pcie_host_init,
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};
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static int __init add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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static int __init exynos_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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@ -615,7 +607,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
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goto fail_bus_clk;
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}
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ret = add_pcie_port(pp, pdev);
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ret = exynos_add_pcie_port(pp, pdev);
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if (ret < 0)
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goto fail_bus_clk;
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@ -656,11 +648,11 @@ static struct platform_driver exynos_pcie_driver = {
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/* Exynos PCIe driver does not allow module unload */
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static int __init pcie_init(void)
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static int __init exynos_pcie_init(void)
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{
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return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
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}
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subsys_initcall(pcie_init);
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subsys_initcall(exynos_pcie_init);
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MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
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MODULE_DESCRIPTION("Samsung PCIe host controller driver");
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@ -32,7 +32,7 @@ struct gen_pci_cfg_bus_ops {
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struct gen_pci_cfg_windows {
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struct resource res;
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struct resource bus_range;
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struct resource *bus_range;
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void __iomem **win;
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const struct gen_pci_cfg_bus_ops *ops;
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@ -50,7 +50,7 @@ static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct gen_pci *pci = sys->private_data;
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resource_size_t idx = bus->number - pci->cfg.bus_range.start;
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resource_size_t idx = bus->number - pci->cfg.bus_range->start;
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return pci->cfg.win[idx] + ((devfn << 8) | where);
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}
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@ -66,7 +66,7 @@ static void __iomem *gen_pci_map_cfg_bus_ecam(struct pci_bus *bus,
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct gen_pci *pci = sys->private_data;
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resource_size_t idx = bus->number - pci->cfg.bus_range.start;
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resource_size_t idx = bus->number - pci->cfg.bus_range->start;
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return pci->cfg.win[idx] + ((devfn << 12) | where);
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}
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@ -138,106 +138,50 @@ static const struct of_device_id gen_pci_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, gen_pci_of_match);
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static int gen_pci_calc_io_offset(struct device *dev,
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struct of_pci_range *range,
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struct resource *res,
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resource_size_t *offset)
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{
|
||||
static atomic_t wins = ATOMIC_INIT(0);
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int err, idx, max_win;
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unsigned int window;
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if (!PAGE_ALIGNED(range->cpu_addr))
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return -EINVAL;
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||||
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||||
max_win = (IO_SPACE_LIMIT + 1) / SZ_64K;
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idx = atomic_inc_return(&wins);
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||||
if (idx > max_win)
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return -ENOSPC;
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||||
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||||
window = (idx - 1) * SZ_64K;
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err = pci_ioremap_io(window, range->cpu_addr);
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||||
if (err)
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||||
return err;
|
||||
|
||||
of_pci_range_to_resource(range, dev->of_node, res);
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res->start = window;
|
||||
res->end = res->start + range->size - 1;
|
||||
*offset = window - range->pci_addr;
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||||
return 0;
|
||||
}
|
||||
|
||||
static int gen_pci_calc_mem_offset(struct device *dev,
|
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struct of_pci_range *range,
|
||||
struct resource *res,
|
||||
resource_size_t *offset)
|
||||
{
|
||||
of_pci_range_to_resource(range, dev->of_node, res);
|
||||
*offset = range->cpu_addr - range->pci_addr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gen_pci_release_of_pci_ranges(struct gen_pci *pci)
|
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{
|
||||
struct pci_host_bridge_window *win;
|
||||
|
||||
list_for_each_entry(win, &pci->resources, list)
|
||||
release_resource(win->res);
|
||||
|
||||
pci_free_resource_list(&pci->resources);
|
||||
}
|
||||
|
||||
static int gen_pci_parse_request_of_pci_ranges(struct gen_pci *pci)
|
||||
{
|
||||
struct of_pci_range range;
|
||||
struct of_pci_range_parser parser;
|
||||
int err, res_valid = 0;
|
||||
struct device *dev = pci->host.dev.parent;
|
||||
struct device_node *np = dev->of_node;
|
||||
resource_size_t iobase;
|
||||
struct pci_host_bridge_window *win;
|
||||
|
||||
if (of_pci_range_parser_init(&parser, np)) {
|
||||
dev_err(dev, "missing \"ranges\" property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
|
||||
&iobase);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
struct resource *parent, *res;
|
||||
resource_size_t offset;
|
||||
u32 restype = range.flags & IORESOURCE_TYPE_BITS;
|
||||
list_for_each_entry(win, &pci->resources, list) {
|
||||
struct resource *parent, *res = win->res;
|
||||
|
||||
res = devm_kmalloc(dev, sizeof(*res), GFP_KERNEL);
|
||||
if (!res) {
|
||||
err = -ENOMEM;
|
||||
goto out_release_res;
|
||||
}
|
||||
|
||||
switch (restype) {
|
||||
switch (resource_type(res)) {
|
||||
case IORESOURCE_IO:
|
||||
parent = &ioport_resource;
|
||||
err = gen_pci_calc_io_offset(dev, &range, res, &offset);
|
||||
err = pci_remap_iospace(res, iobase);
|
||||
if (err) {
|
||||
dev_warn(dev, "error %d: failed to map resource %pR\n",
|
||||
err, res);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
case IORESOURCE_MEM:
|
||||
parent = &iomem_resource;
|
||||
err = gen_pci_calc_mem_offset(dev, &range, res, &offset);
|
||||
res_valid |= !(res->flags & IORESOURCE_PREFETCH || err);
|
||||
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
|
||||
break;
|
||||
case IORESOURCE_BUS:
|
||||
pci->cfg.bus_range = res;
|
||||
default:
|
||||
err = -EINVAL;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (err) {
|
||||
dev_warn(dev,
|
||||
"error %d: failed to add resource [type 0x%x, %lld bytes]\n",
|
||||
err, restype, range.size);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = request_resource(parent, res);
|
||||
err = devm_request_resource(dev, parent, res);
|
||||
if (err)
|
||||
goto out_release_res;
|
||||
|
||||
pci_add_resource_offset(&pci->resources, res, offset);
|
||||
}
|
||||
|
||||
if (!res_valid) {
|
||||
|
|
@ -262,38 +206,30 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
|
|||
struct device *dev = pci->host.dev.parent;
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
if (of_pci_parse_bus_range(np, &pci->cfg.bus_range))
|
||||
pci->cfg.bus_range = (struct resource) {
|
||||
.name = np->name,
|
||||
.start = 0,
|
||||
.end = 0xff,
|
||||
.flags = IORESOURCE_BUS,
|
||||
};
|
||||
|
||||
err = of_address_to_resource(np, 0, &pci->cfg.res);
|
||||
if (err) {
|
||||
dev_err(dev, "missing \"reg\" property\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
pci->cfg.win = devm_kcalloc(dev, resource_size(&pci->cfg.bus_range),
|
||||
/* Limit the bus-range to fit within reg */
|
||||
bus_max = pci->cfg.bus_range->start +
|
||||
(resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
|
||||
pci->cfg.bus_range->end = min_t(resource_size_t,
|
||||
pci->cfg.bus_range->end, bus_max);
|
||||
|
||||
pci->cfg.win = devm_kcalloc(dev, resource_size(pci->cfg.bus_range),
|
||||
sizeof(*pci->cfg.win), GFP_KERNEL);
|
||||
if (!pci->cfg.win)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Limit the bus-range to fit within reg */
|
||||
bus_max = pci->cfg.bus_range.start +
|
||||
(resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
|
||||
pci->cfg.bus_range.end = min_t(resource_size_t, pci->cfg.bus_range.end,
|
||||
bus_max);
|
||||
|
||||
/* Map our Configuration Space windows */
|
||||
if (!devm_request_mem_region(dev, pci->cfg.res.start,
|
||||
resource_size(&pci->cfg.res),
|
||||
"Configuration Space"))
|
||||
return -ENOMEM;
|
||||
|
||||
bus_range = &pci->cfg.bus_range;
|
||||
bus_range = pci->cfg.bus_range;
|
||||
for (busn = bus_range->start; busn <= bus_range->end; ++busn) {
|
||||
u32 idx = busn - bus_range->start;
|
||||
u32 sz = 1 << pci->cfg.ops->bus_shift;
|
||||
|
|
@ -305,8 +241,6 @@ static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Register bus resource */
|
||||
pci_add_resource(&pci->resources, bus_range);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -526,8 +526,8 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
|
|||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, pp->msi_irq,
|
||||
imx6_pcie_msi_handler,
|
||||
IRQF_SHARED, "mx6-pcie-msi", pp);
|
||||
imx6_pcie_msi_handler,
|
||||
IRQF_SHARED, "mx6-pcie-msi", pp);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request MSI irq\n");
|
||||
return -ENODEV;
|
||||
|
|
|
|||
|
|
@ -201,7 +201,7 @@ static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
|
|||
return 0;
|
||||
}
|
||||
|
||||
const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
|
||||
static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
|
||||
.map = ks_dw_pcie_msi_map,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -353,10 +353,9 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
|
||||
GFP_KERNEL);
|
||||
if (!ks_pcie) {
|
||||
dev_err(dev, "no memory for keystone pcie\n");
|
||||
if (!ks_pcie)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pp = &ks_pcie->pp;
|
||||
|
||||
/* initialize SerDes Phy if present */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* PCIe host controller driver for Freescale Layerscape SoCs
|
||||
*
|
||||
* Copyright (C) 2014 Freescale Semiconductor.
|
||||
*
|
||||
* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/resource.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
/* PEX1/2 Misc Ports Status Register */
|
||||
#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
|
||||
#define LTSSM_STATE_SHIFT 20
|
||||
#define LTSSM_STATE_MASK 0x3f
|
||||
#define LTSSM_PCIE_L0 0x11 /* L0 state */
|
||||
|
||||
/* Symbol Timer Register and Filter Mask Register 1 */
|
||||
#define PCIE_STRFMR1 0x71c
|
||||
|
||||
struct ls_pcie {
|
||||
struct list_head node;
|
||||
struct device *dev;
|
||||
struct pci_bus *bus;
|
||||
void __iomem *dbi;
|
||||
struct regmap *scfg;
|
||||
struct pcie_port pp;
|
||||
int index;
|
||||
int msi_irq;
|
||||
};
|
||||
|
||||
#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
|
||||
|
||||
static int ls_pcie_link_up(struct pcie_port *pp)
|
||||
{
|
||||
u32 state;
|
||||
struct ls_pcie *pcie = to_ls_pcie(pp);
|
||||
|
||||
regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
|
||||
state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
|
||||
|
||||
if (state < LTSSM_PCIE_L0)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void ls_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct ls_pcie *pcie = to_ls_pcie(pp);
|
||||
int count = 0;
|
||||
u32 val;
|
||||
|
||||
dw_pcie_setup_rc(pp);
|
||||
|
||||
while (!ls_pcie_link_up(pp)) {
|
||||
usleep_range(100, 1000);
|
||||
count++;
|
||||
if (count >= 200) {
|
||||
dev_err(pp->dev, "phy link never came up\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* LS1021A Workaround for internal TKT228622
|
||||
* to fix the INTx hang issue
|
||||
*/
|
||||
val = ioread32(pcie->dbi + PCIE_STRFMR1);
|
||||
val &= 0xffff;
|
||||
iowrite32(val, pcie->dbi + PCIE_STRFMR1);
|
||||
}
|
||||
|
||||
static struct pcie_host_ops ls_pcie_host_ops = {
|
||||
.link_up = ls_pcie_link_up,
|
||||
.host_init = ls_pcie_host_init,
|
||||
};
|
||||
|
||||
static int ls_add_pcie_port(struct ls_pcie *pcie)
|
||||
{
|
||||
struct pcie_port *pp;
|
||||
int ret;
|
||||
|
||||
pp = &pcie->pp;
|
||||
pp->dev = pcie->dev;
|
||||
pp->dbi_base = pcie->dbi;
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &ls_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(pp->dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init ls_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ls_pcie *pcie;
|
||||
struct resource *dbi_base;
|
||||
u32 index[2];
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->dev = &pdev->dev;
|
||||
|
||||
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
|
||||
if (!dbi_base) {
|
||||
dev_err(&pdev->dev, "missing *regs* space\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
|
||||
if (IS_ERR(pcie->dbi))
|
||||
return PTR_ERR(pcie->dbi);
|
||||
|
||||
pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"fsl,pcie-scfg");
|
||||
if (IS_ERR(pcie->scfg)) {
|
||||
dev_err(&pdev->dev, "No syscfg phandle specified\n");
|
||||
return PTR_ERR(pcie->scfg);
|
||||
}
|
||||
|
||||
ret = of_property_read_u32_array(pdev->dev.of_node,
|
||||
"fsl,pcie-scfg", index, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
pcie->index = index[1];
|
||||
|
||||
ret = ls_add_pcie_port(pcie);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id ls_pcie_of_match[] = {
|
||||
{ .compatible = "fsl,ls1021a-pcie" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
|
||||
|
||||
static struct platform_driver ls_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "layerscape-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = ls_pcie_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
|
||||
|
||||
MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
|
||||
MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -622,6 +622,7 @@ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
|
|||
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = &pcie->ports[i];
|
||||
|
||||
if (bus->number == 0 && port->devfn == devfn)
|
||||
return port;
|
||||
if (bus->number != 0 &&
|
||||
|
|
@ -751,6 +752,7 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
|
|||
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = &pcie->ports[i];
|
||||
|
||||
if (!port->base)
|
||||
continue;
|
||||
mvebu_pcie_setup_hw(port);
|
||||
|
|
|
|||
|
|
@ -380,6 +380,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
|
|||
/* Get the I/O and memory ranges from DT */
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
|
||||
|
||||
if (restype == IORESOURCE_IO) {
|
||||
of_pci_range_to_resource(&range, np, &pp->io);
|
||||
pp->io.name = "I/O";
|
||||
|
|
|
|||
|
|
@ -389,7 +389,7 @@ static void rcar_pcie_add_bus(struct pci_bus *bus)
|
|||
}
|
||||
}
|
||||
|
||||
struct hw_pci rcar_pci = {
|
||||
static struct hw_pci rcar_pci = {
|
||||
.setup = rcar_pcie_setup,
|
||||
.map_irq = of_irq_parse_and_map_pci,
|
||||
.ops = &rcar_pcie_ops,
|
||||
|
|
|
|||
|
|
@ -269,7 +269,8 @@ static struct pcie_host_ops spear13xx_pcie_host_ops = {
|
|||
.host_init = spear13xx_pcie_host_init,
|
||||
};
|
||||
|
||||
static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
|
||||
static int __init spear13xx_add_pcie_port(struct pcie_port *pp,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
|
@ -308,10 +309,8 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
|
|||
int ret;
|
||||
|
||||
spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
|
||||
if (!spear13xx_pcie) {
|
||||
dev_err(dev, "no memory for SPEAr13xx pcie\n");
|
||||
if (!spear13xx_pcie)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
|
||||
if (IS_ERR(spear13xx_pcie->phy)) {
|
||||
|
|
@ -352,7 +351,7 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
|
|||
if (of_property_read_bool(np, "st,pcie-is-gen1"))
|
||||
spear13xx_pcie->is_gen1 = true;
|
||||
|
||||
ret = add_pcie_port(pp, pdev);
|
||||
ret = spear13xx_add_pcie_port(pp, pdev);
|
||||
if (ret < 0)
|
||||
goto fail_clk;
|
||||
|
||||
|
|
@ -382,11 +381,11 @@ static struct platform_driver spear13xx_pcie_driver __initdata = {
|
|||
|
||||
/* SPEAr13xx PCIe driver does not allow module unload */
|
||||
|
||||
static int __init pcie_init(void)
|
||||
static int __init spear13xx_pcie_init(void)
|
||||
{
|
||||
return platform_driver_register(&spear13xx_pcie_driver);
|
||||
}
|
||||
module_init(pcie_init);
|
||||
module_init(spear13xx_pcie_init);
|
||||
|
||||
MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
|
||||
MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
|
||||
|
|
|
|||
Loading…
Reference in New Issue