drm/i915/guc: Split out the mmio_white_list struct
We are going to need it for future platforms. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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@ -1049,11 +1049,11 @@ static int guc_ads_create(struct intel_guc *guc)
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/* MMIO reg state */
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for_each_engine(engine, dev_priv, id) {
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blob->reg_state.mmio_white_list[engine->guc_id].mmio_start =
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blob->reg_state.white_list[engine->guc_id].mmio_start =
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engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
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/* Nothing to be saved or restored for now. */
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blob->reg_state.mmio_white_list[engine->guc_id].count = 0;
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blob->reg_state.white_list[engine->guc_id].count = 0;
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}
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/*
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@ -409,16 +409,17 @@ struct guc_mmio_regset {
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u32 number_of_registers;
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} __packed;
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/* MMIO registers that are set as non privileged */
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struct mmio_white_list {
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u32 mmio_start;
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u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
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u32 count;
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} __packed;
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struct guc_mmio_reg_state {
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struct guc_mmio_regset global_reg;
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struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
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/* MMIO registers that are set as non privileged */
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struct __packed {
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u32 mmio_start;
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u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
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u32 count;
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} mmio_white_list[GUC_MAX_ENGINES_NUM];
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struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
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} __packed;
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/* GuC Additional Data Struct */
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