arm: dts: rockchip: add reset node for the exist saradc SoCs
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -197,6 +197,8 @@
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clock-names = "saradc", "apb_pclk";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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@ -279,6 +279,8 @@
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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@ -399,6 +399,8 @@
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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