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Second Round of Renesas ARM Based SoC DT Updates for v4.8

Browse source 
* Use APMU on R-Car Gen2 and provide SMP for r8a7793 SoC
 * Update console parameters to uniformly use chosen/stdout-path,
   serial0, not provide kernel unnecessary command line parameters
 * Add DU pins to silk board
 * Add support for blanche/r8a7792
 * Name pfc subnodes after device name
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Merge tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM Based SoC DT Updates for v4.8

* Use APMU on R-Car Gen2 and provide SMP for r8a7793 SoC
* Update console parameters to uniformly use chosen/stdout-path,
  serial0, not provide kernel unnecessary command line parameters
* Add DU pins to silk board
* Add support for blanche/r8a7792
* Name pfc subnodes after device name

* tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (41 commits)
  ARM: dts: r8a7792: add SMP support
  ARM: dts: r8a7793: Add APMU node and second CPU core
  ARM: dts: r8a7791: Add APMU node
  ARM: dts: r8a7790: Add APMU nodes
  devicetree: bindings: Renesas APMU and SMP Enable method
  ARM: dts: kzm9g: Update console parameters
  ARM: dts: kzm9d: Update console parameters
  ARM: dts: marzen: Add serial port config to chosen/stdout-path
  ARM: dts: genmai: Update console parameters
  ARM: dts: armadillo800eva: Update console parameters
  ARM: dts: r8a7792: add JPU support
  ARM: dts: r8a7792: add JPU clocks
  ARM: dts: silk: add DU pins
  ARM: dts: blanche: add Ethernet support
  ARM: dts: blanche: initial device tree
  ARM: dts: blanche: document Blanche board
  ARM: dts: r8a7792: add IRQC support
  ARM: dts: r8a7792: add [H]SCIF support
  ARM: dts: r8a7792: add SYS-DMAC support
  ARM: dts: r8a7792: initial SoC device tree
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-07-06 22:11:20 -07:00
parent 46e6b3aa65 8fd763c75c
commit 5fd70b1b17
24 changed files with 695 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.txt
View file

@ -206,6 +206,7 @@ nodes to be present and contain the properties described below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"

2
Documentation/devicetree/bindings/arm/shmobile.txt
View file

@ -39,6 +39,8 @@ Boards:
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)

31
Documentation/devicetree/bindings/power/renesas,apmu.txt Normal file
View file

@ -0,0 +1,31 @@
DT bindings for the Renesas Advanced Power Management Unit
Renesas R-Car line of SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.
Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
- "renesas,r8a7793-apmu" (R-Car M2-N)
- "renesas,r8a7794-apmu" (R-Car E2)
- reg: Base address and length of the I/O registers used by the APMU.
- cpus: This node contains a list of CPU cores, which should match the order
of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
Management Unit section of the device's datasheet.
Example:
This shows the r8a7791 APMU that can control CPU0 and CPU1.
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};

1
arch/arm/boot/dts/Makefile
View file

@ -653,6 +653,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \

8
arch/arm/boot/dts/emev2-kzm9d.dts
View file

@ -23,9 +23,13 @@
reg = <0x40000000 0x8000000>;
};
aliases {
serial1 = &uart1;
};
chosen {
bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
stdout-path = &uart1;
bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp";
stdout-path = "serial1:115200n8";
};
gpio_keys {

4
arch/arm/boot/dts/r7s72100-genmai.dts
View file

@ -17,12 +17,12 @@
compatible = "renesas,genmai", "renesas,r7s72100";
aliases {
serial2 = &scif2;
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = &scif2;
stdout-path = "serial0:115200n8";
};
memory@8000000 {

4
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View file

@ -188,12 +188,12 @@
};
&pfc {
scifa0_pins: serial0 {
scifa0_pins: scifa0 {
groups = "scifa0_data";
function = "scifa0";
};
mmc0_pins: mmc {
mmc0_pins: mmc0 {
groups = "mmc0_data8", "mmc0_ctrl";
function = "mmc0";
};

8
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View file

@ -20,12 +20,12 @@
compatible = "renesas,armadillo800eva", "renesas,r8a7740";
aliases {
serial1 = &scifa1;
serial0 = &scifa1;
};
chosen {
bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
stdout-path = &scifa1;
bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
@ -232,7 +232,7 @@
function = "gether";
};
scifa1_pins: serial1 {
scifa1_pins: scifa1 {
groups = "scifa1_data";
function = "scifa1";
};

2
arch/arm/boot/dts/r8a7778-bockw.dts
View file

@ -129,7 +129,7 @@
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: serial0 {
scif0_pins: scif0 {
groups = "scif0_data_a", "scif0_ctrl";
function = "scif0";
};

6
arch/arm/boot/dts/r8a7779-marzen.dts
View file

@ -25,7 +25,7 @@
chosen {
bootargs = "ignore_loglevel root=/dev/nfs ip=on";
stdout-path = &scif2;
stdout-path = "serial0:115200n8";
};
memory@60000000 {
@ -195,12 +195,12 @@
};
};
scif2_pins: serial2 {
scif2_pins: scif2 {
groups = "scif2_data_c";
function = "scif2";
};
scif4_pins: serial4 {
scif4_pins: scif4 {
groups = "scif4_data";
function = "scif4";
};

10
arch/arm/boot/dts/r8a7790-lager.dts
View file

@ -317,7 +317,7 @@
function = "du";
};
scif0_pins: serial0 {
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
@ -337,7 +337,7 @@
function = "intc";
};
scifa1_pins: serial1 {
scifa1_pins: scifa1 {
groups = "scifa1_data";
function = "scifa1";
};
@ -371,12 +371,12 @@
function = "mmc1";
};
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof1_pins: spi2 {
msiof1_pins: msiof1 {
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
"msiof1_tx";
function = "msiof1";
@ -427,7 +427,7 @@
function = "usb2";
};
vin1_pins: vin {
vin1_pins: vin1 {
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};

13
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -44,6 +44,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -164,6 +165,18 @@
};
};
apmu@e6151000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6151000 0 0x188>;
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
apmu@e6152000 {
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

8
arch/arm/boot/dts/r8a7791-koelsch.dts
View file

@ -332,12 +332,12 @@
function = "du";
};
scif0_pins: serial0 {
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
scif1_pins: scif1 {
groups = "scif1_data_d";
function = "scif1";
};
@ -372,12 +372,12 @@
function = "sdhi2";
};
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof0_pins: spi1 {
msiof0_pins: msiof0 {
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
"msiof0_tx";
function = "msiof0";

4
arch/arm/boot/dts/r8a7791-porter.dts
View file

@ -142,7 +142,7 @@
};
&pfc {
scif0_pins: serial0 {
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
@ -167,7 +167,7 @@
function = "sdhi2";
};
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};

7
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -43,6 +43,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -101,6 +102,12 @@
};
};
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

66
arch/arm/boot/dts/r8a7792-blanche.dts Normal file
View file

@ -0,0 +1,66 @@
/*
* Device Tree Source for the Blanche board
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7792.dtsi"
/ {
model = "Blanche";
compatible = "renesas,blanche", "renesas,r8a7792";
aliases {
serial0 = &scif0;
serial1 = &scif3;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
d3_3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ethernet@18000000 {
compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0 0x18000000 0 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqc>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
smsc,irq-push-pull;
reg-io-width = <4>;
vddvario-supply = <&d3_3v>;
vdd33a-supply = <&d3_3v>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif0 {
status = "okay";
};
&scif3 {
status = "okay";
};

378
arch/arm/boot/dts/r8a7792.dtsi Normal file
View file

@ -0,0 +1,378 @@
/*
* Device Tree Source for the r8a7792 SoC
*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a7792-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7792-sysc.h>
/ {
compatible = "renesas,r8a7792";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
L2_CA15: cache-controller@0 {
compatible = "cache";
reg = <0>;
cache-unified;
cache-level = <2>;
power-domains = <&sysc R8A7792_PD_CA15_SCU>;
};
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
<0 0xf1002000 0 0x1000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7792", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
#power-domain-cells = <1>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <15>;
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e58000 0 64>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
scif3: serial@e6ea8000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ea8000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
hscif0: serial@e62c0000 {
compatible = "renesas,hscif-r8a7792",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c0000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
<&dmac1 0x39>, <&dmac1 0x3a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
hscif1: serial@e62c8000 {
compatible = "renesas,hscif-r8a7792",
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c8000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
<&dmac1 0x4d>, <&dmac1 0x4e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
status = "disabled";
};
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7792",
"renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_JPU>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "z", "adsp";
#power-domain-cells = <0>;
};
/* Fixed factor clocks */
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
};
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
};
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
};
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
};
/* Gate clocks */
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&m2_clk>;
#clock-cells = <1>;
clock-indices = <R8A7792_CLK_JPU>;
clock-output-names = "jpu";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
clocks = <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
>;
clock-output-names = "sys-dmac1", "sys-dmac0";
};
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>;
#clock-cells = <1>;
clock-indices = <R8A7792_CLK_IRQC>;
clock-output-names = "irqc";
};
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
<&p_clk>, <&p_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
>;
clock-output-names = "hscif1", "hscif0", "scif3",
"scif2", "scif1", "scif0";
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
};

6
arch/arm/boot/dts/r8a7793-gose.dts
View file

@ -320,12 +320,12 @@
function = "du";
};
scif0_pins: serial0 {
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
scif1_pins: scif1 {
groups = "scif1_data_d";
function = "scif1";
};
@ -360,7 +360,7 @@
renesas,function = "sdhi2";
};
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};

15
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -35,6 +35,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -56,6 +57,14 @@
next-level-cache = <&L2_CA15>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
};
L2_CA15: cache-controller@0 {
compatible = "cache";
reg = <0>;
@ -65,6 +74,12 @@
};
};
apmu@e6152000 {
compatible = "renesas,r8a7793-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;

4
arch/arm/boot/dts/r8a7794-alt.dts
View file

@ -111,7 +111,7 @@
function = "du";
};
scif2_pins: serial2 {
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
@ -147,7 +147,7 @@
};
&pfc {
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};

16
arch/arm/boot/dts/r8a7794-silk.dts
View file

@ -129,7 +129,7 @@
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: serial2 {
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
@ -164,7 +164,7 @@
function = "sdhi1";
};
qspi_pins: spi0 {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
@ -183,6 +183,16 @@
groups = "usb1";
function = "usb1";
};
du0_pins: du0 {
groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
function = "du0";
};
du1_pins: du1 {
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
function = "du1";
};
};
&scif2 {
@ -360,6 +370,8 @@
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,

8
arch/arm/boot/dts/sh73a0-kzm9g.dts
View file

@ -22,7 +22,7 @@
compatible = "renesas,kzm9g", "renesas,sh73a0";
aliases {
serial4 = &scifa4;
serial0 = &scifa4;
};
cpus {
@ -39,8 +39,8 @@
};
chosen {
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
stdout-path = &scifa4;
bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
@ -352,7 +352,7 @@
};
};
scifa4_pins: serial4 {
scifa4_pins: scifa4 {
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};

103
include/dt-bindings/clock/r8a7792-clock.h Normal file
View file

@ -0,0 +1,103 @@
/*
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
#define __DT_BINDINGS_CLOCK_R8A7792_H__
/* CPG */
#define R8A7792_CLK_MAIN 0
#define R8A7792_CLK_PLL0 1
#define R8A7792_CLK_PLL1 2
#define R8A7792_CLK_PLL3 3
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
#define R8A7792_CLK_Z 6
#define R8A7792_CLK_ADSP 7
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7792_CLK_JPU 6
#define R8A7792_CLK_TMU1 11
#define R8A7792_CLK_TMU3 21
#define R8A7792_CLK_TMU2 22
#define R8A7792_CLK_CMT0 24
#define R8A7792_CLK_TMU0 25
#define R8A7792_CLK_VSP1DU1 27
#define R8A7792_CLK_VSP1DU0 28
#define R8A7792_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7792_CLK_MSIOF1 8
#define R8A7792_CLK_SYS_DMAC1 18
#define R8A7792_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7792_CLK_TPU0 4
#define R8A7792_CLK_SDHI0 14
#define R8A7792_CLK_CMT1 29
/* MSTP4 */
#define R8A7792_CLK_IRQC 7
/* MSTP5 */
#define R8A7792_CLK_AUDIO_DMAC0 2
#define R8A7792_CLK_THERMAL 22
#define R8A7792_CLK_PWM 23
/* MSTP7 */
#define R8A7792_CLK_HSCIF1 16
#define R8A7792_CLK_HSCIF0 17
#define R8A7792_CLK_SCIF3 18
#define R8A7792_CLK_SCIF2 19
#define R8A7792_CLK_SCIF1 20
#define R8A7792_CLK_SCIF0 21
#define R8A7792_CLK_DU1 23
#define R8A7792_CLK_DU0 24
/* MSTP8 */
#define R8A7792_CLK_VIN5 4
#define R8A7792_CLK_VIN4 5
#define R8A7792_CLK_VIN3 8
#define R8A7792_CLK_VIN2 9
#define R8A7792_CLK_VIN1 10
#define R8A7792_CLK_VIN0 11
#define R8A7792_CLK_ETHERAVB 12
/* MSTP9 */
#define R8A7792_CLK_GPIO7 4
#define R8A7792_CLK_GPIO6 5
#define R8A7792_CLK_GPIO5 7
#define R8A7792_CLK_GPIO4 8
#define R8A7792_CLK_GPIO3 9
#define R8A7792_CLK_GPIO2 10
#define R8A7792_CLK_GPIO1 11
#define R8A7792_CLK_GPIO0 12
#define R8A7792_CLK_GPIO11 13
#define R8A7792_CLK_GPIO10 14
#define R8A7792_CLK_CAN1 15
#define R8A7792_CLK_CAN0 16
#define R8A7792_CLK_QSPI_MOD 17
#define R8A7792_CLK_GPIO9 19
#define R8A7792_CLK_GPIO8 21
#define R8A7792_CLK_I2C5 25
#define R8A7792_CLK_IICDVFS 26
#define R8A7792_CLK_I2C4 27
#define R8A7792_CLK_I2C3 28
#define R8A7792_CLK_I2C2 29
#define R8A7792_CLK_I2C1 30
#define R8A7792_CLK_I2C0 31
/* MSTP10 */
#define R8A7792_CLK_SSI_ALL 5
#define R8A7792_CLK_SSI4 11
#define R8A7792_CLK_SSI3 12
#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */

26
include/dt-bindings/power/r8a7792-sysc.h Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7792_PD_CA15_CPU0 0
#define R8A7792_PD_CA15_CPU1 1
#define R8A7792_PD_CA15_SCU 12
#define R8A7792_PD_SGX 20
#define R8A7792_PD_IMP 24
/* Always-on power area */
#define R8A7792_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */