drm/i915: Assorted INTEL_INFO(dev) cleanups
A bunch of source files with just a few instances of the incorrect INTEL_INFO use. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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29b74b7f17
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66478475b5
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@ -95,8 +95,7 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
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static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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{
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struct drm_crtc *crtc = crtc_state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int i, pipe = intel_crtc->pipe;
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uint16_t coeffs[9] = { 0, };
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@ -180,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
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if (INTEL_INFO(dev)->gen > 6) {
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if (INTEL_GEN(dev_priv) > 6) {
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uint16_t postoff = 0;
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if (intel_crtc_state->limited_color_range)
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@ -147,14 +147,13 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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int mode)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_crt *crt = intel_encoder_to_crt(encoder);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
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u32 adpa;
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if (INTEL_INFO(dev)->gen >= 5)
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if (INTEL_GEN(dev_priv) >= 5)
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adpa = ADPA_HOTPLUG_BITS;
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else
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adpa = 0;
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@ -673,8 +672,7 @@ static const struct dmi_system_id intel_spurious_crt_detect[] = {
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static enum drm_connector_status
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intel_crt_detect(struct drm_connector *connector, bool force)
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{
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struct drm_device *dev = connector->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(connector->dev);
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struct intel_crt *crt = intel_attached_crt(connector);
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struct intel_encoder *intel_encoder = &crt->base;
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enum intel_display_power_domain power_domain;
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@ -731,7 +729,7 @@ intel_crt_detect(struct drm_connector *connector, bool force)
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if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
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if (intel_crt_detect_ddc(connector))
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status = connector_status_connected;
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else if (INTEL_INFO(dev)->gen < 4)
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else if (INTEL_GEN(dev_priv) < 4)
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status = intel_crt_load_detect(crt,
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to_intel_crtc(connector->state->crtc)->pipe);
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else if (i915.load_detect_test)
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@ -793,11 +791,10 @@ static int intel_crt_set_property(struct drm_connector *connector,
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void intel_crt_reset(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
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if (INTEL_INFO(dev)->gen >= 5) {
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if (INTEL_GEN(dev_priv) >= 5) {
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u32 adpa;
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adpa = I915_READ(crt->adpa_reg);
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@ -1753,8 +1753,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
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struct drm_connector_state *old_conn_state)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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uint32_t val;
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@ -1787,7 +1786,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
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DPLL_CTRL2_DDI_CLK_OFF(port)));
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else if (INTEL_INFO(dev)->gen < 9)
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else if (INTEL_GEN(dev_priv) < 9)
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I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
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if (type == INTEL_OUTPUT_HDMI) {
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@ -1837,8 +1836,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_crtc *crtc = encoder->crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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@ -1856,7 +1854,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder,
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} else if (type == INTEL_OUTPUT_EDP) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
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if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
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intel_dp_stop_link_train(intel_dp);
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intel_edp_backlight_on(intel_dp);
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@ -188,13 +188,12 @@ out:
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void intel_disable_shared_dpll(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll = crtc->config->shared_dpll;
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unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
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/* PCH only available on ILK+ */
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if (INTEL_INFO(dev)->gen < 5)
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if (INTEL_GEN(dev_priv) < 5)
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return;
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if (pll == NULL)
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@ -122,8 +122,7 @@ out:
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static void intel_lvds_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
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u32 tmp, flags = 0;
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@ -139,12 +138,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
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pipe_config->base.adjusted_mode.flags |= flags;
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if (INTEL_INFO(dev)->gen < 5)
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if (INTEL_GEN(dev_priv) < 5)
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pipe_config->gmch_pfit.lvds_border_bits =
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tmp & LVDS_BORDER_ENABLE;
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/* gen2/3 store dither state in pfit control, needs to match */
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if (INTEL_INFO(dev)->gen < 4) {
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if (INTEL_GEN(dev_priv) < 4) {
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tmp = I915_READ(PFIT_CONTROL);
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pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
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@ -304,7 +304,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *pipe_config,
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int fitting_mode)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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@ -325,7 +325,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
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break;
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case DRM_MODE_SCALE_ASPECT:
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/* Scale but preserve the aspect ratio */
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if (INTEL_INFO(dev)->gen >= 4)
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if (INTEL_GEN(dev_priv) >= 4)
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i965_scale_aspect(pipe_config, &pfit_control);
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else
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i9xx_scale_aspect(pipe_config, &pfit_control,
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@ -339,7 +339,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
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if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
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pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
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pfit_control |= PFIT_ENABLE;
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if (INTEL_INFO(dev)->gen >= 4)
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if (INTEL_GEN(dev_priv) >= 4)
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pfit_control |= PFIT_SCALING_AUTO;
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else
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pfit_control |= (VERT_AUTO_SCALE |
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@ -355,7 +355,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
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/* 965+ wants fuzzy fitting */
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/* FIXME: handle multiple panels by failing gracefully */
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if (INTEL_INFO(dev)->gen >= 4)
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if (INTEL_GEN(dev_priv) >= 4)
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pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
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PFIT_FILTER_FUZZY);
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@ -366,7 +366,7 @@ out:
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}
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/* Make sure pre-965 set dither correctly for 18bpp panels. */
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if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
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if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
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pfit_control |= PANEL_8TO6_DITHER_ENABLE;
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pipe_config->gmch_pfit.control = pfit_control;
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@ -472,7 +472,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
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/* Enable PSR on the panel */
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hsw_psr_enable_sink(intel_dp);
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if (INTEL_INFO(dev)->gen >= 9)
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if (INTEL_GEN(dev_priv) >= 9)
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intel_psr_activate(intel_dp);
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} else {
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vlv_psr_setup_vsc(intel_dp);
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@ -498,7 +498,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
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* - On HSW/BDW we get a recoverable frozen screen until next
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* exit-activate sequence.
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*/
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if (INTEL_INFO(dev)->gen < 9)
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if (INTEL_GEN(dev_priv) < 9)
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schedule_delayed_work(&dev_priv->psr.work,
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msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
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@ -1195,8 +1195,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct drm_device *dev = intel_encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
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struct drm_display_mode *mode = &crtc_state->base.mode;
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@ -1269,13 +1268,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
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return;
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/* Set the SDVO control regs. */
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if (INTEL_INFO(dev)->gen >= 4) {
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if (INTEL_GEN(dev_priv) >= 4) {
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/* The real mode polarity is set by the SDVO commands, using
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* struct intel_sdvo_dtd. */
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sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
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if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
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sdvox |= HDMI_COLOR_RANGE_16_235;
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if (INTEL_INFO(dev)->gen < 5)
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if (INTEL_GEN(dev_priv) < 5)
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sdvox |= SDVO_BORDER_ENABLE;
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} else {
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sdvox = I915_READ(intel_sdvo->sdvo_reg);
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@ -1294,7 +1293,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
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if (intel_sdvo->has_hdmi_audio)
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sdvox |= SDVO_AUDIO_ENABLE;
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if (INTEL_INFO(dev)->gen >= 4) {
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if (INTEL_GEN(dev_priv) >= 4) {
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/* done in crtc_mode_set as the dpll_md reg must be written early */
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} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
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IS_G33(dev_priv)) {
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@ -1305,7 +1304,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
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}
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if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
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INTEL_INFO(dev)->gen < 5)
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INTEL_GEN(dev_priv) < 5)
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sdvox |= SDVO_STALL_SELECT;
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intel_sdvo_write_sdvox(intel_sdvo, sdvox);
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}
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@ -1029,8 +1029,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_tv *intel_tv = enc_to_tv(encoder);
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const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
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@ -1116,7 +1115,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
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set_color_conversion(dev_priv, color_conversion);
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if (INTEL_INFO(dev)->gen >= 4)
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if (INTEL_GEN(dev_priv) >= 4)
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I915_WRITE(TV_CLR_KNOBS, 0x00404000);
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else
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I915_WRITE(TV_CLR_KNOBS, 0x00606000);
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@ -1483,7 +1483,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
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for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
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if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
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(INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
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(INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
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break;
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}
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