ARM: pxa168: correct nand pmu setting
The original pair of <0x01db, 208000000> is invalid. Correct it to the valid value. The 6th bit of the NFC APMU register indicates NFC works whether at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and 0x1db indicates it works at 78Mhz. Signed-off-by: Lei Wen <leiwen@marvell.com> Cc: stable@kernel.org Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
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static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
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static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
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static APMU_CLK(nand, NAND, 0x01db, 208000000);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(lcd, LCD, 0x7f, 312000000);
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/* device and clock bindings */
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