clk: samsung: exynos7: Correct CMU_FSYS1 clocks names
This patch renames CMU_FSYS1 clocks names to match with user manual. And also adds missing gate clock for aclk_fsys1_200. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -515,6 +515,8 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
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ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
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ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
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@ -957,9 +959,9 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
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/*
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* List of parent clocks for Muxes in CMU_FSYS1
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*/
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PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
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PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
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PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
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PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
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PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
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PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
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static unsigned long fsys1_clk_regs[] __initdata = {
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MUX_SEL_FSYS10,
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@ -968,11 +970,13 @@ static unsigned long fsys1_clk_regs[] __initdata = {
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};
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static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
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MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
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MUX_SEL_FSYS10, 28, 1),
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MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
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MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
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MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
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MUX_SEL_FSYS11, 24, 1),
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MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
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MUX_SEL_FSYS11, 28, 1),
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};
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static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
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@ -63,7 +63,8 @@
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#define CLK_SCLK_MMC1 7
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#define CLK_SCLK_MMC0 8
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#define CLK_ACLK_FSYS0_200 9
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#define TOP1_NR_CLK 10
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#define CLK_ACLK_FSYS1_200 10
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#define TOP1_NR_CLK 11
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/* CCORE */
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#define PCLK_RTC 1
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