PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc() programs the Root Complex registers. The Root Complex may lose power during suspend-to-RAM, and when we resume, we want to redo the latter but not the former. Move some Root Complex programming from dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call dw_pcie_setup_rc() in their resume paths. [Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the dra7xx pp->mem_base update before calling dw_pcie_setup_rc().] [bhelgaas: changelog, fold in dra7xx fix from Niklas] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
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static void dra7xx_pcie_host_init(struct pcie_port *pp)
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static void dra7xx_pcie_host_init(struct pcie_port *pp)
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{
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{
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dw_pcie_setup_rc(pp);
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pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
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dw_pcie_setup_rc(pp);
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dra7xx_pcie_establish_link(pp);
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dra7xx_pcie_establish_link(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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dw_pcie_msi_init(pp);
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@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct pci_bus *bus, *child;
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struct pci_bus *bus, *child;
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struct resource *cfg_res;
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struct resource *cfg_res;
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u32 val;
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int i, ret;
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int i, ret;
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LIST_HEAD(res);
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LIST_HEAD(res);
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struct resource_entry *win;
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struct resource_entry *win;
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@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
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if (pp->ops->host_init)
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if (pp->ops->host_init)
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pp->ops->host_init(pp);
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pp->ops->host_init(pp);
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/*
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* If the platform provides ->rd_other_conf, it means the platform
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* uses its own address translation component rather than ATU, so
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* we should not program the ATU here.
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*/
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if (!pp->ops->rd_other_conf)
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_MEM, pp->mem_base,
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pp->mem_bus_addr, pp->mem_size);
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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/* program correct class for RC */
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dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
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val |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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pp->root_bus_nr = pp->busn->start;
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pp->root_bus_nr = pp->busn->start;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
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bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
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@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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dw_pcie_writel_rc(pp, val, PCI_COMMAND);
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dw_pcie_writel_rc(pp, val, PCI_COMMAND);
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/*
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* If the platform provides ->rd_other_conf, it means the platform
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* uses its own address translation component rather than ATU, so
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* we should not program the ATU here.
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*/
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if (!pp->ops->rd_other_conf)
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_MEM, pp->mem_base,
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pp->mem_bus_addr, pp->mem_size);
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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/* program correct class for RC */
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dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
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val |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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}
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}
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MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
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MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
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