[ARM] OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond
Richard Woodruff writes that chip errata prevent USBTLL SAR from working on OMAP3 ES levels before ES3.1: http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2 Update the OMAP3 powerdomain structures appropriately. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
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&iva2_pwrdm,
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&mpu_34xx_pwrdm,
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&neon_pwrdm,
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&core_34xx_pwrdm,
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&core_34xx_pre_es3_1_pwrdm,
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&core_34xx_es3_1_pwrdm,
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&cam_pwrdm,
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&dss_pwrdm,
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&per_pwrdm,
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@ -200,10 +200,12 @@ static struct powerdomain mpu_34xx_pwrdm = {
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};
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/* No wkdeps or sleepdeps for 34xx core apparently */
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static struct powerdomain core_34xx_pwrdm = {
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static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
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CHIP_IS_OMAP3430ES2 |
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CHIP_IS_OMAP3430ES3_0),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.banks = 2,
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@ -217,6 +219,25 @@ static struct powerdomain core_34xx_pwrdm = {
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},
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};
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/* No wkdeps or sleepdeps for 34xx core apparently */
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static struct powerdomain core_34xx_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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/* Another case of bit name collisions between several registers: EN_DSS */
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static struct powerdomain dss_pwrdm = {
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.name = "dss_pwrdm",
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