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clk: tegra: Set the clk parent of host1x to pll_p

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The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
This commit is contained in:
Andrew Chew 2013-08-07 19:25:09 +08:00 committed by Peter De Schrijver
parent 252d0d2bb0
commit 897e1dde1e
1 changed files with 1 additions and 0 deletions
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drivers/clk/tegra/clk-tegra114.c
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@ -2183,6 +2183,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0},