Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "One drm core fix, one exynos regression fix, two sets of radeon fixes (Alex was a bit behind last week), and two i915 fixes. Nothing too serious we seem to have calmed down i915 since last week" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: fix wait in radeon_mn_invalidate_range_start drm/radeon: add extra check in radeon_ttm_tt_unpin_userptr drm: Exynos: Respect framebuffer pitch for FIMD/Mixer drm/i915: Reject the colorkey ioctls for primary and cursor planes drm/i915: Skip allocating shadow batch for 0-length batches drm/radeon: programm the VCE fw BAR as well drm/radeon: always dump the ring content if it's available radeon: Do not directly dereference pointers to BIOS area. drm/radeon/dpm: fix 120hz handling harder drm/edid: set ELD for firmware and debugfs override EDIDs
This commit is contained in:
commit
8f778bbc54
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@ -287,6 +287,7 @@ int drm_load_edid_firmware(struct drm_connector *connector)
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drm_mode_connector_update_edid_property(connector, edid);
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ret = drm_add_edid_modes(connector, edid);
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drm_edid_to_eld(connector, edid);
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kfree(edid);
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return ret;
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@ -174,6 +174,7 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
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struct edid *edid = (struct edid *) connector->edid_blob_ptr->data;
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count = drm_add_edid_modes(connector, edid);
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drm_edid_to_eld(connector, edid);
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} else
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count = (*connector_funcs->get_modes)(connector);
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}
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@ -147,6 +147,7 @@ struct fimd_win_data {
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unsigned int ovl_height;
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unsigned int fb_width;
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unsigned int fb_height;
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unsigned int fb_pitch;
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unsigned int bpp;
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unsigned int pixel_format;
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dma_addr_t dma_addr;
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@ -532,13 +533,14 @@ static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
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win_data->offset_y = plane->crtc_y;
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win_data->ovl_width = plane->crtc_width;
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win_data->ovl_height = plane->crtc_height;
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win_data->fb_pitch = plane->pitch;
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win_data->fb_width = plane->fb_width;
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win_data->fb_height = plane->fb_height;
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win_data->dma_addr = plane->dma_addr[0] + offset;
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win_data->bpp = plane->bpp;
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win_data->pixel_format = plane->pixel_format;
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win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
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(plane->bpp >> 3);
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win_data->buf_offsize =
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plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
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win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
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DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
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@ -704,7 +706,7 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
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writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
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/* buffer end address */
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size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
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size = win_data->fb_pitch * win_data->ovl_height * (win_data->bpp >> 3);
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val = (unsigned long)(win_data->dma_addr + size);
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writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
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@ -55,6 +55,7 @@ struct hdmi_win_data {
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unsigned int fb_x;
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unsigned int fb_y;
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unsigned int fb_width;
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unsigned int fb_pitch;
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unsigned int fb_height;
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unsigned int src_width;
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unsigned int src_height;
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@ -438,7 +439,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
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} else {
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luma_addr[0] = win_data->dma_addr;
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chroma_addr[0] = win_data->dma_addr
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+ (win_data->fb_width * win_data->fb_height);
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+ (win_data->fb_pitch * win_data->fb_height);
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}
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if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) {
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@ -447,8 +448,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
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luma_addr[1] = luma_addr[0] + 0x40;
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chroma_addr[1] = chroma_addr[0] + 0x40;
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} else {
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luma_addr[1] = luma_addr[0] + win_data->fb_width;
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chroma_addr[1] = chroma_addr[0] + win_data->fb_width;
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luma_addr[1] = luma_addr[0] + win_data->fb_pitch;
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chroma_addr[1] = chroma_addr[0] + win_data->fb_pitch;
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}
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} else {
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ctx->interlace = false;
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@ -469,10 +470,10 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
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vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
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/* setting size of input image */
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vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) |
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vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_pitch) |
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VP_IMG_VSIZE(win_data->fb_height));
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/* chroma height has to reduced by 2 to avoid chroma distorions */
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vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) |
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vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_pitch) |
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VP_IMG_VSIZE(win_data->fb_height / 2));
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vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width);
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@ -559,7 +560,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
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/* converting dma address base and source offset */
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dma_addr = win_data->dma_addr
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+ (win_data->fb_x * win_data->bpp >> 3)
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+ (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3);
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+ (win_data->fb_y * win_data->fb_pitch);
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src_x_offset = 0;
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src_y_offset = 0;
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@ -576,7 +577,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
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MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
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/* setup geometry */
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mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
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mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
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win_data->fb_pitch / (win_data->bpp >> 3));
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/* setup display size */
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if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
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@ -961,6 +963,7 @@ static void mixer_win_mode_set(struct exynos_drm_crtc *crtc,
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win_data->fb_y = plane->fb_y;
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win_data->fb_width = plane->fb_width;
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win_data->fb_height = plane->fb_height;
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win_data->fb_pitch = plane->pitch;
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win_data->src_width = plane->src_width;
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win_data->src_height = plane->src_height;
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@ -1487,7 +1487,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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goto err;
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}
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if (i915_needs_cmd_parser(ring)) {
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if (i915_needs_cmd_parser(ring) && args->batch_len) {
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batch_obj = i915_gem_execbuffer_parse(ring,
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&shadow_exec_entry,
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eb,
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@ -1322,7 +1322,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
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drm_modeset_lock_all(dev);
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plane = drm_plane_find(dev, set->plane_id);
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if (!plane) {
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if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) {
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ret = -ENOENT;
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goto out_unlock;
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}
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@ -1349,7 +1349,7 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
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drm_modeset_lock_all(dev);
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plane = drm_plane_find(dev, get->plane_id);
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if (!plane) {
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if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) {
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ret = -ENOENT;
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goto out_unlock;
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}
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@ -2129,6 +2129,7 @@
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#define VCE_UENC_REG_CLOCK_GATING 0x207c0
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#define VCE_SYS_INT_EN 0x21300
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# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
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#define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
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#define VCE_LMI_CTRL2 0x21474
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#define VCE_LMI_CTRL 0x21498
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#define VCE_LMI_VM_CTRL 0x214a0
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@ -1565,6 +1565,7 @@ struct radeon_dpm {
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int new_active_crtc_count;
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u32 current_active_crtcs;
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int current_active_crtc_count;
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bool single_display;
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struct radeon_dpm_dynamic_state dyn_state;
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struct radeon_dpm_fan fan;
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u32 tdp_limit;
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@ -76,7 +76,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
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static bool radeon_read_bios(struct radeon_device *rdev)
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{
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uint8_t __iomem *bios;
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uint8_t __iomem *bios, val1, val2;
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size_t size;
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rdev->bios = NULL;
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@ -86,15 +86,19 @@ static bool radeon_read_bios(struct radeon_device *rdev)
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return false;
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}
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if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
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val1 = readb(&bios[0]);
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val2 = readb(&bios[1]);
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if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
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pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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rdev->bios = kmemdup(bios, size, GFP_KERNEL);
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rdev->bios = kzalloc(size, GFP_KERNEL);
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if (rdev->bios == NULL) {
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pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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memcpy_fromio(rdev->bios, bios, size);
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pci_unmap_rom(rdev->pdev, bios);
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return true;
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}
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@ -122,7 +122,6 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
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it = interval_tree_iter_first(&rmn->objects, start, end);
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while (it) {
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struct radeon_bo *bo;
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struct fence *fence;
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int r;
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bo = container_of(it, struct radeon_bo, mn_it);
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continue;
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}
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fence = reservation_object_get_excl(bo->tbo.resv);
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if (fence) {
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r = radeon_fence_wait((struct radeon_fence *)fence, false);
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if (r)
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DRM_ERROR("(%d) failed to wait for user bo\n", r);
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}
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r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true,
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false, MAX_SCHEDULE_TIMEOUT);
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if (r)
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DRM_ERROR("(%d) failed to wait for user bo\n", r);
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radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU);
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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@ -837,12 +837,8 @@ static void radeon_dpm_thermal_work_handler(struct work_struct *work)
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radeon_pm_compute_clocks(rdev);
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}
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static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state)
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static bool radeon_dpm_single_display(struct radeon_device *rdev)
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{
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int i;
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struct radeon_ps *ps;
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u32 ui_class;
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bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
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true : false;
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@ -858,6 +854,17 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
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single_display = false;
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return single_display;
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}
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static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state)
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{
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int i;
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struct radeon_ps *ps;
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u32 ui_class;
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bool single_display = radeon_dpm_single_display(rdev);
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/* certain older asics have a separare 3D performance state,
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* so try that first if the user selected performance
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*/
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@ -983,6 +990,7 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
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struct radeon_ps *ps;
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enum radeon_pm_state_type dpm_state;
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int ret;
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bool single_display = radeon_dpm_single_display(rdev);
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/* if dpm init failed */
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if (!rdev->pm.dpm_enabled)
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@ -1007,6 +1015,9 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
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/* vce just modifies an existing state so force a change */
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if (ps->vce_active != rdev->pm.dpm.vce_active)
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goto force;
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/* user has made a display change (such as timing) */
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if (rdev->pm.dpm.single_display != single_display)
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goto force;
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if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
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/* for pre-BTC and APUs if the num crtcs changed but state is the same,
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* all we need to do is update the display configuration.
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@ -1069,6 +1080,7 @@ force:
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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@ -495,7 +495,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
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seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
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seq_printf(m, "%u dwords in ring\n", count);
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if (!ring->ready)
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if (!ring->ring)
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return 0;
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/* print 8 dw before current rptr as often it's the last executed
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@ -598,6 +598,10 @@ static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
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enum dma_data_direction direction = write ?
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DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
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/* double check that we don't free the table twice */
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if (!ttm->sg->sgl)
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return;
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/* free the sg table and pages again */
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dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
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@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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addr &= 0xff;
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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Loading…
Reference in a new issue