Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
Pull thermal management fixes from Zhang Rui: "These includes several commits that are necessary to properly fix regression for TMU test MUX address setting after reset, for exynos thermal driver. Specifics: - fix a regression that the removal of setting a certain field at TMU configuration setting results in immediately shutdown after reset on Exynos4412 SoC. - revert a patch which tries to link the thermal_zone device and its hwmon node but breaks libsensors. - fix a deadlock/lockdep warning issue in x86_pkg_temp thermal driver, which can be reproduced on a buggy platform only. - fix ti-soc-thermal driver to fall back on bandgap reading when reading from PCB temperature sensor fails" * 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: Revert "drivers: thermal: parent virtual hwmon with thermal zone" drivers: thermal: allow ti-soc-thermal run without pcb zone thermal: exynos: Provide initial setting for TMU's test MUX address at Exynos4412 thermal: exynos: Provide separate TMU data for Exynos4412 thermal: exynos: Remove check for thermal device pointer at exynos_report_trigger() Thermal: x86_pkg_temp: change spin lock
This commit is contained in:
commit
90338325a9
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@ -310,8 +310,6 @@ void exynos_report_trigger(struct thermal_sensor_conf *conf)
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}
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}
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th_zone = conf->pzone_data;
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th_zone = conf->pzone_data;
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if (th_zone->therm_dev)
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return;
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if (th_zone->bind == false) {
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if (th_zone->bind == false) {
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for (i = 0; i < th_zone->cool_dev_size; i++) {
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for (i = 0; i < th_zone->cool_dev_size; i++) {
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@ -317,6 +317,9 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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con = readl(data->base + reg->tmu_ctrl);
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con = readl(data->base + reg->tmu_ctrl);
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if (pdata->test_mux)
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con |= (pdata->test_mux << reg->test_mux_addr_shift);
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if (pdata->reference_voltage) {
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if (pdata->reference_voltage) {
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con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
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con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
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con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
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con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
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@ -488,7 +491,7 @@ static const struct of_device_id exynos_tmu_match[] = {
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},
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},
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{
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{
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.compatible = "samsung,exynos4412-tmu",
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.compatible = "samsung,exynos4412-tmu",
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.data = (void *)EXYNOS5250_TMU_DRV_DATA,
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.data = (void *)EXYNOS4412_TMU_DRV_DATA,
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},
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},
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{
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{
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.compatible = "samsung,exynos5250-tmu",
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.compatible = "samsung,exynos5250-tmu",
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@ -629,9 +632,10 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (pdata->type == SOC_ARCH_EXYNOS ||
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if (pdata->type == SOC_ARCH_EXYNOS4210 ||
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pdata->type == SOC_ARCH_EXYNOS4210 ||
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pdata->type == SOC_ARCH_EXYNOS4412 ||
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pdata->type == SOC_ARCH_EXYNOS5440)
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pdata->type == SOC_ARCH_EXYNOS5250 ||
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pdata->type == SOC_ARCH_EXYNOS5440)
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data->soc = pdata->type;
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data->soc = pdata->type;
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else {
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else {
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ret = -EINVAL;
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ret = -EINVAL;
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@ -41,7 +41,8 @@ enum calibration_mode {
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enum soc_type {
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enum soc_type {
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SOC_ARCH_EXYNOS4210 = 1,
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SOC_ARCH_EXYNOS4210 = 1,
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SOC_ARCH_EXYNOS,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5440,
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SOC_ARCH_EXYNOS5440,
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};
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};
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@ -84,6 +85,7 @@ enum soc_type {
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* @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
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* @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
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reg.
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reg.
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* @tmu_ctrl: TMU main controller register.
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* @tmu_ctrl: TMU main controller register.
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* @test_mux_addr_shift: shift bits of test mux address.
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* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
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* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
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* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
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* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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@ -150,6 +152,7 @@ struct exynos_tmu_registers {
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u32 triminfo_reload_shift;
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u32 triminfo_reload_shift;
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u32 tmu_ctrl;
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u32 tmu_ctrl;
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u32 test_mux_addr_shift;
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u32 buf_vref_sel_shift;
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u32 buf_vref_sel_shift;
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u32 buf_vref_sel_mask;
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u32 buf_vref_sel_mask;
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u32 therm_trip_mode_shift;
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u32 therm_trip_mode_shift;
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@ -257,6 +260,7 @@ struct exynos_tmu_registers {
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* @first_point_trim: temp value of the first point trimming
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* @first_point_trim: temp value of the first point trimming
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* @second_point_trim: temp value of the second point trimming
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* @second_point_trim: temp value of the second point trimming
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* @default_temp_offset: default temperature offset in case of no trimming
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* @default_temp_offset: default temperature offset in case of no trimming
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* @test_mux; information if SoC supports test MUX
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* @cal_type: calibration type for temperature
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* @cal_type: calibration type for temperature
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* @cal_mode: calibration mode for temperature
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* @cal_mode: calibration mode for temperature
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* @freq_clip_table: Table representing frequency reduction percentage.
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* @freq_clip_table: Table representing frequency reduction percentage.
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@ -286,6 +290,7 @@ struct exynos_tmu_platform_data {
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u8 first_point_trim;
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u8 first_point_trim;
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u8 second_point_trim;
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u8 second_point_trim;
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u8 default_temp_offset;
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u8 default_temp_offset;
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u8 test_mux;
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enum calibration_type cal_type;
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enum calibration_type cal_type;
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enum calibration_mode cal_mode;
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enum calibration_mode cal_mode;
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@ -90,14 +90,15 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos5250_tmu_registers = {
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
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.triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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@ -128,7 +129,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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};
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#define EXYNOS5250_TMU_DATA \
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#define EXYNOS4412_TMU_DATA \
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.threshold_falling = 10, \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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.trigger_levels[0] = 85, \
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.trigger_levels[1] = 103, \
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.trigger_levels[1] = 103, \
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@ -162,15 +163,32 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
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.temp_level = 103, \
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.temp_level = 103, \
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}, \
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}, \
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.freq_tab_count = 2, \
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.freq_tab_count = 2, \
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.type = SOC_ARCH_EXYNOS, \
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.registers = &exynos4412_tmu_registers, \
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.registers = &exynos5250_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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TMU_SUPPORT_EMUL_TIME)
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412)
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struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS4412,
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.test_mux = EXYNOS4412_MUX_ADDR_VALUE,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250)
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struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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.tmu_data = {
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.tmu_data = {
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{ EXYNOS5250_TMU_DATA },
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS5250,
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},
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},
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},
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.tmu_count = 1,
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.tmu_count = 1,
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};
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};
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@ -95,6 +95,10 @@
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#define EXYNOS_MAX_TRIGGER_PER_REG 4
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#define EXYNOS_MAX_TRIGGER_PER_REG 4
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/* Exynos4412 specific */
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#define EXYNOS4412_MUX_ADDR_VALUE 6
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#define EXYNOS4412_MUX_ADDR_SHIFT 20
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/*exynos5440 specific registers*/
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/*exynos5440 specific registers*/
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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@ -138,7 +142,14 @@ extern struct exynos_tmu_init_data const exynos4210_default_tmu_data;
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#define EXYNOS4210_TMU_DRV_DATA (NULL)
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#define EXYNOS4210_TMU_DRV_DATA (NULL)
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#endif
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#endif
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#if (defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412))
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#if defined(CONFIG_SOC_EXYNOS4412)
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extern struct exynos_tmu_init_data const exynos4412_default_tmu_data;
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#define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data)
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#else
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#define EXYNOS4412_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250)
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extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
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extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
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#define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
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#define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
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#else
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#else
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@ -159,7 +159,7 @@ int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
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INIT_LIST_HEAD(&hwmon->tz_list);
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INIT_LIST_HEAD(&hwmon->tz_list);
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strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH);
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strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH);
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hwmon->device = hwmon_device_register(&tz->device);
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hwmon->device = hwmon_device_register(NULL);
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if (IS_ERR(hwmon->device)) {
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if (IS_ERR(hwmon->device)) {
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result = PTR_ERR(hwmon->device);
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result = PTR_ERR(hwmon->device);
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goto free_mem;
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goto free_mem;
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@ -110,6 +110,7 @@ static inline int ti_thermal_get_temp(struct thermal_zone_device *thermal,
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} else {
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} else {
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dev_err(bgp->dev,
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dev_err(bgp->dev,
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"Failed to read PCB state. Using defaults\n");
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"Failed to read PCB state. Using defaults\n");
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ret = 0;
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}
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}
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}
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}
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*temp = ti_thermal_hotspot_temperature(tmp, slope, constant);
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*temp = ti_thermal_hotspot_temperature(tmp, slope, constant);
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|
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@ -316,18 +316,19 @@ static void pkg_temp_thermal_threshold_work_fn(struct work_struct *work)
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int phy_id = topology_physical_package_id(cpu);
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int phy_id = topology_physical_package_id(cpu);
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struct phy_dev_entry *phdev = pkg_temp_thermal_get_phy_entry(cpu);
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struct phy_dev_entry *phdev = pkg_temp_thermal_get_phy_entry(cpu);
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bool notify = false;
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bool notify = false;
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unsigned long flags;
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if (!phdev)
|
if (!phdev)
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return;
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return;
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spin_lock(&pkg_work_lock);
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spin_lock_irqsave(&pkg_work_lock, flags);
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++pkg_work_cnt;
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++pkg_work_cnt;
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if (unlikely(phy_id > max_phy_id)) {
|
if (unlikely(phy_id > max_phy_id)) {
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spin_unlock(&pkg_work_lock);
|
spin_unlock_irqrestore(&pkg_work_lock, flags);
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return;
|
return;
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}
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}
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pkg_work_scheduled[phy_id] = 0;
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pkg_work_scheduled[phy_id] = 0;
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spin_unlock(&pkg_work_lock);
|
spin_unlock_irqrestore(&pkg_work_lock, flags);
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|
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enable_pkg_thres_interrupt();
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enable_pkg_thres_interrupt();
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rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
|
rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
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@ -397,6 +398,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu)
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int thres_count;
|
int thres_count;
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u32 eax, ebx, ecx, edx;
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u32 eax, ebx, ecx, edx;
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u8 *temp;
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u8 *temp;
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unsigned long flags;
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|
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cpuid(6, &eax, &ebx, &ecx, &edx);
|
cpuid(6, &eax, &ebx, &ecx, &edx);
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thres_count = ebx & 0x07;
|
thres_count = ebx & 0x07;
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|
@ -420,19 +422,19 @@ static int pkg_temp_thermal_device_add(unsigned int cpu)
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goto err_ret_unlock;
|
goto err_ret_unlock;
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||||||
}
|
}
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||||||
|
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||||||
spin_lock(&pkg_work_lock);
|
spin_lock_irqsave(&pkg_work_lock, flags);
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if (topology_physical_package_id(cpu) > max_phy_id)
|
if (topology_physical_package_id(cpu) > max_phy_id)
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max_phy_id = topology_physical_package_id(cpu);
|
max_phy_id = topology_physical_package_id(cpu);
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||||||
temp = krealloc(pkg_work_scheduled,
|
temp = krealloc(pkg_work_scheduled,
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(max_phy_id+1) * sizeof(u8), GFP_ATOMIC);
|
(max_phy_id+1) * sizeof(u8), GFP_ATOMIC);
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||||||
if (!temp) {
|
if (!temp) {
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spin_unlock(&pkg_work_lock);
|
spin_unlock_irqrestore(&pkg_work_lock, flags);
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err = -ENOMEM;
|
err = -ENOMEM;
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goto err_ret_free;
|
goto err_ret_free;
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||||||
}
|
}
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pkg_work_scheduled = temp;
|
pkg_work_scheduled = temp;
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pkg_work_scheduled[topology_physical_package_id(cpu)] = 0;
|
pkg_work_scheduled[topology_physical_package_id(cpu)] = 0;
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||||||
spin_unlock(&pkg_work_lock);
|
spin_unlock_irqrestore(&pkg_work_lock, flags);
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||||||
|
|
||||||
phy_dev_entry->phys_proc_id = topology_physical_package_id(cpu);
|
phy_dev_entry->phys_proc_id = topology_physical_package_id(cpu);
|
||||||
phy_dev_entry->first_cpu = cpu;
|
phy_dev_entry->first_cpu = cpu;
|
||||||
|
|
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