MLK-18046 ARM64: dts: pass-through edma0 channel14/15 and lpuart1
Passthrough EDMA0 Channel 14/15 and lpuart1 to DomU. Delete the original edma0 node and introduce the other 5 nodes to which contains two channels each node. Currently the nodes are included in fsl-imx8qm-xen.dtsi. The modem-reset node to support bluetooth is not introduced in DomU dts, because gpio support has not been done. Signed-off-by: Peng Fan <peng.fan@nxp.com>pull/10/head
parent
bde8425bac
commit
97768a9306
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@ -74,6 +74,9 @@
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SC_R_SDHC_0
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SC_R_SDHC_0
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SC_R_USB_0
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SC_R_USB_0
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SC_R_USB_0_PHY
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SC_R_USB_0_PHY
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SC_R_UART_1
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SC_R_DMA_0_CH14
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SC_R_DMA_0_CH15
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SC_R_MU_2A
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SC_R_MU_2A
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>;
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>;
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pads = <
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pads = <
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@ -92,6 +95,12 @@
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SC_P_EMMC0_RESET_B
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SC_P_EMMC0_RESET_B
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/* usb otg */
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/* usb otg */
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SC_P_USB_SS3_TC0
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SC_P_USB_SS3_TC0
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/* uart1 */
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SC_P_UART1_RX
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SC_P_UART1_TX
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SC_P_UART1_CTS_B
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SC_P_UART1_RTS_B
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SC_P_QSPI1A_DQS
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>;
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>;
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};
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};
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};
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};
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@ -132,6 +141,10 @@
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xen,passthrough;
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xen,passthrough;
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};
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};
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&lpuart1 {
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xen,passthrough;
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};
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&lpuart1_lpcg {
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&lpuart1_lpcg {
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xen,passthrough;
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xen,passthrough;
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};
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};
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@ -144,15 +157,23 @@
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xen,passthrough;
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xen,passthrough;
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};
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};
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&edma01 {
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#stream-id-cells = <1>;
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xen,passthrough;
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fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>,
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<SC_R_DMA_0_CH15>;
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};
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/* SMMU */
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/* SMMU */
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&smmu {
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&smmu {
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mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>,
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mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>,
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<&usdhc1 0x12>, <&usbotg1 0x11>;
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<&usdhc1 0x12>, <&usbotg1 0x11>,
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<&edma01 0x10>;
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};
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};
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/* DC0 */
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/* DC0 */
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&pd_dc1 {
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&pd_dc1 {
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xen,passthrogh;
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xen,passthrough;
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};
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};
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&lvds_region2 {
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&lvds_region2 {
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@ -36,6 +36,7 @@
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mmc0 = &usdhc1;
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mmc0 = &usdhc1;
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dpu1 = &dpu2;
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dpu1 = &dpu2;
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ldb1 = &ldb2;
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ldb1 = &ldb2;
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serial1 = &lpuart1;
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};
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};
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passthrough {
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passthrough {
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@ -68,6 +69,17 @@
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reg = <0x1 0x5b270000 0x0 0x10000>;
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reg = <0x1 0x5b270000 0x0 0x10000>;
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};
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};
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edma01: dma-controller1@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x1 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
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<0x1 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx";
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status = "okay";
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};
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};
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};
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};
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};
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@ -275,7 +287,16 @@
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/delete-node/ &i2c0_mipi_csi1;
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/delete-node/ &i2c0_mipi_csi1;
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/delete-node/ &lpspi0;
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/delete-node/ &lpspi0;
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/delete-node/ &lpuart0;
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/delete-node/ &lpuart0;
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/delete-node/ &lpuart1;
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&lpuart1 {
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/delete-property/ interrupt-parent;
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reg = <0x1 0x5a070000 0 0x1000>;
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dmas = <&edma01 15 0 0>, <&edma01 14 0 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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/delete-node/ &lpuart2;
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/delete-node/ &lpuart2;
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/delete-node/ &lpuart3;
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/delete-node/ &lpuart3;
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/delete-node/ &lpuart4;
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/delete-node/ &lpuart4;
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@ -455,8 +476,15 @@
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>;
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>;
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};
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};
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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SC_P_UART1_RX_DMA_UART1_RX 0x06000020
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SC_P_UART1_TX_DMA_UART1_TX 0x06000020
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SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
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SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
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SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021
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>;
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};
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};
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};
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};
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};
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@ -20,6 +20,66 @@
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/delete-node/ wu;
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/delete-node/ wu;
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edma00: dma-controller0@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
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<0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx";
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status = "okay";
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};
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edma01: dma-controller1@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
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<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx";
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status = "okay";
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};
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edma02: dma-controller2@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
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<0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx";
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status = "okay";
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};
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edma03: dma-controller3@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
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<0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx";
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status = "okay";
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};
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edma04: dma-controller4@5a1f0000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
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<0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
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#dma-cells = <3>;
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dma-channels = <2>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx";
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status = "okay";
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};
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usbotg1_lpcg: usbotg1_lpcg@5b270000 {
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usbotg1_lpcg: usbotg1_lpcg@5b270000 {
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compatible = "fsl,imx8qm-usbotg1-lpcg";
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compatible = "fsl,imx8qm-usbotg1-lpcg";
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reg = <0x0 0x5b270000 0x0 0x10000>;
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reg = <0x0 0x5b270000 0x0 0x10000>;
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@ -56,6 +116,8 @@
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};
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};
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};
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};
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/delete-node/ &edma0;
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&mu {
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&mu {
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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};
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};
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@ -66,18 +128,22 @@
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&lpuart1 {
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&lpuart1 {
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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dmas = <&edma01 15 0 0>, <&edma01 14 0 1>;
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};
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};
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&lpuart2 {
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&lpuart2 {
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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dmas = <&edma02 17 0 0>, <&edma02 16 0 1>;
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};
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};
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&lpuart3 {
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&lpuart3 {
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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dmas = <&edma03 19 0 0>, <&edma03 18 0 1>;
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};
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};
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&lpuart4 {
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&lpuart4 {
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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dmas = <&edma04 21 0 0>, <&edma04 20 0 1>;
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};
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};
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&usdhc1 {
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&usdhc1 {
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