clk/exynos5420: add gate clock for mixer sysmmu
Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -180,6 +180,7 @@ clock which they consume.
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fimc_lite3 495
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aclk_g3d 500
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g3d 501
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smmu_mixer 502
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Example 1: An example of a clock controller node is listed below.
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@ -138,7 +138,7 @@ enum exynos5420_clks {
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aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
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gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
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aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
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smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
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smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
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nr_clks,
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};
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@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
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GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
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GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
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GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
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};
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static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
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