Merge branch 'bgmac'
bgmac: add initial support for core rev 4 on ARM BCM47xx ==================== This adds support for core rev 4 and ARM BCM47XX. With an other fix to the platform code I am now getting over 200 MBit/s with this Ethernet driver, the DMA problems are solved are unrelated to bgmac. v3: - moved flags calculation for bcma_core_enable() into if block - remove hard coding of phy address to BGMAC_PHY_NOREGS v2: add changed suggested by Rafał ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
a1d4b03a07
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@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struct bcma_bus *bus,
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int bcma_bus_suspend(struct bcma_bus *bus);
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int bcma_bus_resume(struct bcma_bus *bus);
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#endif
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struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit);
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/* scan.c */
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int bcma_bus_scan(struct bcma_bus *bus);
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@ -78,18 +78,6 @@ static u16 bcma_cc_core_id(struct bcma_bus *bus)
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return BCMA_CORE_CHIPCOMMON;
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}
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struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
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{
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struct bcma_device *core;
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list_for_each_entry(core, &bus->cores, list) {
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if (core->id.id == coreid)
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return core;
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(bcma_find_core);
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struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit)
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{
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@ -101,6 +89,7 @@ struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(bcma_find_core_unit);
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bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
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int timeout)
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@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct bgmac *bgmac,
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
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if (bgmac->core->id.rev >= 4) {
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ctl &= ~BGMAC_DMA_TX_BL_MASK;
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ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
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ctl &= ~BGMAC_DMA_TX_MR_MASK;
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ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
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ctl &= ~BGMAC_DMA_TX_PC_MASK;
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ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
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ctl &= ~BGMAC_DMA_TX_PT_MASK;
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ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
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}
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ctl |= BGMAC_DMA_TX_ENABLE;
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ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
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@ -240,6 +253,16 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac,
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
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if (bgmac->core->id.rev >= 4) {
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ctl &= ~BGMAC_DMA_RX_BL_MASK;
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ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
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ctl &= ~BGMAC_DMA_RX_PC_MASK;
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ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
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ctl &= ~BGMAC_DMA_RX_PT_MASK;
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ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
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}
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ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
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ctl |= BGMAC_DMA_RX_ENABLE;
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ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
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@ -745,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
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u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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u32 new_val = (cmdcfg & mask) | set;
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bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
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bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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if (new_val != cmdcfg || force)
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bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
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bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
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bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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}
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@ -825,6 +848,9 @@ static void bgmac_mac_speed(struct bgmac *bgmac)
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case SPEED_1000:
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set |= BGMAC_CMDCFG_ES_1000;
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break;
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case SPEED_2500:
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set |= BGMAC_CMDCFG_ES_2500;
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break;
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default:
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bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
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}
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@ -837,12 +863,26 @@ static void bgmac_mac_speed(struct bgmac *bgmac)
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static void bgmac_miiconfig(struct bgmac *bgmac)
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{
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u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
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BGMAC_DS_MM_SHIFT;
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if (imode == 0 || imode == 1) {
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bgmac->mac_speed = SPEED_100;
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struct bcma_device *core = bgmac->core;
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struct bcma_chipinfo *ci = &core->bus->chipinfo;
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u8 imode;
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if (ci->id == BCMA_CHIP_ID_BCM4707 ||
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ci->id == BCMA_CHIP_ID_BCM53018) {
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bcma_awrite32(core, BCMA_IOCTL,
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bcma_aread32(core, BCMA_IOCTL) | 0x40 |
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BGMAC_BCMA_IOCTL_SW_CLKEN);
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bgmac->mac_speed = SPEED_2500;
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bgmac->mac_duplex = DUPLEX_FULL;
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bgmac_mac_speed(bgmac);
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} else {
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imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
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BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
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if (imode == 0 || imode == 1) {
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bgmac->mac_speed = SPEED_100;
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bgmac->mac_duplex = DUPLEX_FULL;
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bgmac_mac_speed(bgmac);
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}
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}
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}
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@ -852,7 +892,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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struct bcma_device *core = bgmac->core;
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struct bcma_bus *bus = core->bus;
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struct bcma_chipinfo *ci = &bus->chipinfo;
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u32 flags = 0;
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u32 flags;
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u32 iost;
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int i;
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@ -880,15 +920,21 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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(ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
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iost &= ~BGMAC_BCMA_IOST_ATTACHED;
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if (iost & BGMAC_BCMA_IOST_ATTACHED) {
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flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
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if (!bgmac->has_robosw)
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flags |= BGMAC_BCMA_IOCTL_SW_RESET;
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/* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
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if (ci->id != BCMA_CHIP_ID_BCM4707) {
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flags = 0;
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if (iost & BGMAC_BCMA_IOST_ATTACHED) {
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flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
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if (!bgmac->has_robosw)
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flags |= BGMAC_BCMA_IOCTL_SW_RESET;
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}
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bcma_core_enable(core, flags);
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}
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bcma_core_enable(core, flags);
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if (core->id.rev > 2) {
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/* Request Misc PLL for corerev > 2 */
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if (core->id.rev > 2 &&
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ci->id != BCMA_CHIP_ID_BCM4707 &&
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ci->id != BCMA_CHIP_ID_BCM53018) {
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bgmac_set(bgmac, BCMA_CLKCTLST,
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BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
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bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
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@ -954,7 +1000,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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BGMAC_CMDCFG_PROM |
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BGMAC_CMDCFG_NLC |
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BGMAC_CMDCFG_CFE |
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BGMAC_CMDCFG_SR,
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BGMAC_CMDCFG_SR(core->id.rev),
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false);
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bgmac->mac_speed = SPEED_UNKNOWN;
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bgmac->mac_duplex = DUPLEX_UNKNOWN;
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@ -997,7 +1043,7 @@ static void bgmac_enable(struct bgmac *bgmac)
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cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
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BGMAC_CMDCFG_SR, true);
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BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
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udelay(2);
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cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
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bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
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break;
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}
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rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
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mdp = (bp_clk * 128 / 1000) - 3;
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rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
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bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
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if (ci->id != BCMA_CHIP_ID_BCM4707 &&
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ci->id != BCMA_CHIP_ID_BCM53018) {
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rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
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1000000;
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mdp = (bp_clk * 128 / 1000) - 3;
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rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
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bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
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}
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
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bgmac_chip_reset(bgmac);
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/* For Northstar, we have to take all GMAC core out of reset */
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if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
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core->id.id == BCMA_CHIP_ID_BCM53018) {
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struct bcma_device *ns_core;
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int ns_gmac;
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/* Northstar has 4 GMAC cores */
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for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
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/* As northstar requirement, we have to reset all GAMCs
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* before accessing one. bgmac_chip_reset() call
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* bcma_core_enable() for this core. Then the other
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* three GAMCs didn't reset. We do it here.
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*/
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ns_core = bcma_find_core_unit(core->bus,
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BCMA_CORE_MAC_GBIT,
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ns_gmac);
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if (ns_core && !bcma_core_is_enabled(ns_core))
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bcma_core_enable(ns_core, 0);
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}
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}
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err = bgmac_dma_alloc(bgmac);
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if (err) {
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bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
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@ -189,6 +189,7 @@
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#define BGMAC_CMDCFG_ES_10 0x00000000
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#define BGMAC_CMDCFG_ES_100 0x00000004
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#define BGMAC_CMDCFG_ES_1000 0x00000008
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#define BGMAC_CMDCFG_ES_2500 0x0000000C
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#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
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#define BGMAC_CMDCFG_PAD_EN 0x00000020
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#define BGMAC_CMDCFG_CF 0x00000040
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@ -197,7 +198,9 @@
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#define BGMAC_CMDCFG_TAI 0x00000200
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#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
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#define BGMAC_CMDCFG_HD_SHIFT 10
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#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
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#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
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#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
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#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
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#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
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#define BGMAC_CMDCFG_AE 0x00400000
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#define BGMAC_CMDCFG_CFE 0x00800000
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@ -237,9 +240,34 @@
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#define BGMAC_DMA_TX_SUSPEND 0x00000002
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#define BGMAC_DMA_TX_LOOPBACK 0x00000004
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#define BGMAC_DMA_TX_FLUSH 0x00000010
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#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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#define BGMAC_DMA_TX_MR_SHIFT 6
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#define BGMAC_DMA_TX_MR_1 0
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#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
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#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
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#define BGMAC_DMA_TX_BL_SHIFT 18
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#define BGMAC_DMA_TX_BL_16 0
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#define BGMAC_DMA_TX_BL_32 1
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#define BGMAC_DMA_TX_BL_64 2
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#define BGMAC_DMA_TX_BL_128 3
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#define BGMAC_DMA_TX_BL_256 4
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#define BGMAC_DMA_TX_BL_512 5
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#define BGMAC_DMA_TX_BL_1024 6
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#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
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#define BGMAC_DMA_TX_PC_SHIFT 21
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#define BGMAC_DMA_TX_PC_0 0
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#define BGMAC_DMA_TX_PC_4 1
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#define BGMAC_DMA_TX_PC_8 2
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#define BGMAC_DMA_TX_PC_16 3
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#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
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#define BGMAC_DMA_TX_PT_SHIFT 24
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#define BGMAC_DMA_TX_PT_1 0
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#define BGMAC_DMA_TX_PT_2 1
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#define BGMAC_DMA_TX_PT_4 2
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#define BGMAC_DMA_TX_PT_8 3
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#define BGMAC_DMA_TX_INDEX 0x04
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#define BGMAC_DMA_TX_RINGLO 0x08
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#define BGMAC_DMA_TX_RINGHI 0x0C
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@ -267,8 +295,33 @@
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#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
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#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
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#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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#define BGMAC_DMA_RX_MR_SHIFT 6
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#define BGMAC_DMA_TX_MR_1 0
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#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
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#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
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#define BGMAC_DMA_RX_BL_SHIFT 18
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#define BGMAC_DMA_RX_BL_16 0
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#define BGMAC_DMA_RX_BL_32 1
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#define BGMAC_DMA_RX_BL_64 2
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#define BGMAC_DMA_RX_BL_128 3
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#define BGMAC_DMA_RX_BL_256 4
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#define BGMAC_DMA_RX_BL_512 5
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#define BGMAC_DMA_RX_BL_1024 6
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#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
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#define BGMAC_DMA_RX_PC_SHIFT 21
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#define BGMAC_DMA_RX_PC_0 0
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#define BGMAC_DMA_RX_PC_4 1
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#define BGMAC_DMA_RX_PC_8 2
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#define BGMAC_DMA_RX_PC_16 3
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#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
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#define BGMAC_DMA_RX_PT_SHIFT 24
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#define BGMAC_DMA_RX_PT_1 0
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#define BGMAC_DMA_RX_PT_2 1
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#define BGMAC_DMA_RX_PT_4 2
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#define BGMAC_DMA_RX_PT_8 3
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#define BGMAC_DMA_RX_INDEX 0x24
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#define BGMAC_DMA_RX_RINGLO 0x28
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#define BGMAC_DMA_RX_RINGHI 0x2C
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@ -418,7 +418,14 @@ static inline void bcma_maskset16(struct bcma_device *cc,
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bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
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}
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extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
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extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
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u8 unit);
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static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
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u16 coreid)
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{
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return bcma_find_core_unit(bus, coreid, 0);
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}
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extern bool bcma_core_is_enabled(struct bcma_device *core);
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extern void bcma_core_disable(struct bcma_device *core, u32 flags);
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extern int bcma_core_enable(struct bcma_device *core, u32 flags);
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