powerpc/booke64: Use SPRG_TLB_EXFRAME on bolted handlers
While bolted handlers (including e6500) do not need to deal with a TLB miss recursively causing another TLB miss, nested TLB misses can still happen with crit/mc/debug exceptions -- so we still need to honor SPRG_TLB_EXFRAME. We don't need to spend time modifying it in the TLB miss fastpath, though -- the special level exception will handle that. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Cc: kvm-ppc@vger.kernel.org
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@ -172,16 +172,6 @@ exc_##label##_book3e:
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ld r9,EX_TLB_R9(r12); \
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ld r8,EX_TLB_R8(r12); \
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mtlr r16;
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#define TLB_MISS_PROLOG_STATS_BOLTED \
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mflr r10; \
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std r8,PACA_EXTLB+EX_TLB_R8(r13); \
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std r9,PACA_EXTLB+EX_TLB_R9(r13); \
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std r10,PACA_EXTLB+EX_TLB_LR(r13);
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#define TLB_MISS_RESTORE_STATS_BOLTED \
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ld r16,PACA_EXTLB+EX_TLB_LR(r13); \
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ld r9,PACA_EXTLB+EX_TLB_R9(r13); \
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ld r8,PACA_EXTLB+EX_TLB_R8(r13); \
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mtlr r16;
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#define TLB_MISS_STATS_D(name) \
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addi r9,r13,MMSTAT_DSTATS+name; \
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bl .tlb_stat_inc;
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@ -45,10 +45,12 @@
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*
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* Expected inputs (TLB exception type):
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* r10 = saved CR
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* r12 = extlb pointer
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11
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* SPRN_SPRG_GEN_SCRATCH = saved r13
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* *(r12 + EX_TLB_R10) = saved r10
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* *(r12 + EX_TLB_R11) = saved r11
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* *(r12 + EX_TLB_R13) = saved r13
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* SPRN_SPRG_GEN_SCRATCH = saved r12
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*
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* Only the bolted version of TLB miss exception handlers is supported now.
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*/
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@ -229,13 +229,20 @@
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stw r10, VCPU_CR(r4)
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PPC_STL r11, VCPU_GPR(R4)(r4)
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PPC_STL r5, VCPU_GPR(R5)(r4)
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mfspr r5, \scratch
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PPC_STL r6, VCPU_GPR(R6)(r4)
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PPC_STL r8, VCPU_GPR(R8)(r4)
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PPC_STL r9, VCPU_GPR(R9)(r4)
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PPC_STL r5, VCPU_GPR(R13)(r4)
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.if \type == EX_TLB
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PPC_LL r5, EX_TLB_R13(r12)
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PPC_LL r6, EX_TLB_R10(r12)
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PPC_LL r8, EX_TLB_R11(r12)
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mfspr r12, \scratch
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.else
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mfspr r5, \scratch
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PPC_LL r6, (\paca_ex + \ex_r10)(r13)
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PPC_LL r8, (\paca_ex + \ex_r11)(r13)
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.endif
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PPC_STL r5, VCPU_GPR(R13)(r4)
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PPC_STL r3, VCPU_GPR(R3)(r4)
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PPC_STL r7, VCPU_GPR(R7)(r4)
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PPC_STL r12, VCPU_GPR(R12)(r4)
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@ -39,37 +39,49 @@
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* *
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**********************************************************************/
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/*
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* Note that, unlike non-bolted handlers, TLB_EXFRAME is not
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* modified by the TLB miss handlers themselves, since the TLB miss
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* handler code will not itself cause a recursive TLB miss.
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*
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* TLB_EXFRAME will be modified when crit/mc/debug exceptions are
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* entered/exited.
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*/
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.macro tlb_prolog_bolted intnum addr
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mtspr SPRN_SPRG_GEN_SCRATCH,r13
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mtspr SPRN_SPRG_GEN_SCRATCH,r12
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mfspr r12,SPRN_SPRG_TLB_EXFRAME
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std r13,EX_TLB_R13(r12)
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std r10,EX_TLB_R10(r12)
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mfspr r13,SPRN_SPRG_PACA
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std r10,PACA_EXTLB+EX_TLB_R10(r13)
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mfcr r10
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std r11,PACA_EXTLB+EX_TLB_R11(r13)
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std r11,EX_TLB_R11(r12)
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#ifdef CONFIG_KVM_BOOKE_HV
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BEGIN_FTR_SECTION
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mfspr r11, SPRN_SRR1
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END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
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#endif
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DO_KVM \intnum, SPRN_SRR1
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std r16,PACA_EXTLB+EX_TLB_R16(r13)
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std r16,EX_TLB_R16(r12)
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mfspr r16,\addr /* get faulting address */
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std r14,PACA_EXTLB+EX_TLB_R14(r13)
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std r14,EX_TLB_R14(r12)
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ld r14,PACAPGD(r13)
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std r15,PACA_EXTLB+EX_TLB_R15(r13)
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std r10,PACA_EXTLB+EX_TLB_CR(r13)
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TLB_MISS_PROLOG_STATS_BOLTED
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std r15,EX_TLB_R15(r12)
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std r10,EX_TLB_CR(r12)
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TLB_MISS_PROLOG_STATS
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.endm
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.macro tlb_epilog_bolted
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ld r14,PACA_EXTLB+EX_TLB_CR(r13)
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ld r10,PACA_EXTLB+EX_TLB_R10(r13)
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ld r11,PACA_EXTLB+EX_TLB_R11(r13)
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ld r14,EX_TLB_CR(r12)
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ld r10,EX_TLB_R10(r12)
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ld r11,EX_TLB_R11(r12)
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ld r13,EX_TLB_R13(r12)
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mtcr r14
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ld r14,PACA_EXTLB+EX_TLB_R14(r13)
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ld r15,PACA_EXTLB+EX_TLB_R15(r13)
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TLB_MISS_RESTORE_STATS_BOLTED
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ld r16,PACA_EXTLB+EX_TLB_R16(r13)
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mfspr r13,SPRN_SPRG_GEN_SCRATCH
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ld r14,EX_TLB_R14(r12)
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ld r15,EX_TLB_R15(r12)
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TLB_MISS_RESTORE_STATS
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ld r16,EX_TLB_R16(r12)
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mfspr r12,SPRN_SPRG_GEN_SCRATCH
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.endm
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/* Data TLB miss */
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