Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Radeon and i915 fixes. I probably should have sent these earlier, but nothing too urgent in them: - i915: blackscreen and corruption fixes - radeon: oops, locking and stability" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: add missing crtc unlock when setting up the MC drm/radeon: use gart for DMA IB tests drm/radeon: make sure mode init is complete in bandwidth_update drm/radeon: set correct CE ram size for CIK drm/i915: safeguard against too high minimum brightness drm/i915: vlv: fix gunit HW state corruption during S4 suspend drm/i915: Disable caches for Global GTT.
This commit is contained in:
commit
b3cf93b356
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@ -986,6 +986,15 @@ static int i915_pm_freeze(struct device *dev)
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return i915_drm_freeze(drm_dev);
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}
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static int i915_pm_freeze_late(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct drm_device *drm_dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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return intel_suspend_complete(dev_priv);
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}
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static int i915_pm_thaw_early(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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@ -1570,6 +1579,7 @@ static const struct dev_pm_ops i915_pm_ops = {
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.resume_early = i915_pm_resume_early,
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.resume = i915_pm_resume,
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.freeze = i915_pm_freeze,
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.freeze_late = i915_pm_freeze_late,
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.thaw_early = i915_pm_thaw_early,
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.thaw = i915_pm_thaw,
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.poweroff = i915_pm_poweroff,
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@ -1902,6 +1902,22 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
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GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
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GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
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if (!USES_PPGTT(dev_priv->dev))
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/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
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* so RTL will always use the value corresponding to
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* pat_sel = 000".
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* So let's disable cache for GGTT to avoid screen corruptions.
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* MOCS still can be used though.
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* - System agent ggtt writes (i.e. cpu gtt mmaps) already work
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* before this patch, i.e. the same uncached + snooping access
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* like on gen6/7 seems to be in effect.
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* - So this just fixes blitter/render access. Again it looks
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* like it's not just uncached access, but uncached + snooping.
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* So we can still hold onto all our assumptions wrt cpu
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* clflushing on LLC machines.
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*/
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pat = GEN8_PPAT(0, GEN8_PPAT_UC);
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/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
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* write would work. */
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I915_WRITE(GEN8_PRIVATE_PAT, pat);
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@ -1098,12 +1098,25 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector)
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struct drm_device *dev = connector->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_panel *panel = &connector->panel;
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int min;
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WARN_ON(panel->backlight.max == 0);
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/*
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* XXX: If the vbt value is 255, it makes min equal to max, which leads
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* to problems. There are such machines out there. Either our
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* interpretation is wrong or the vbt has bogus data. Or both. Safeguard
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* against this by letting the minimum be at most (arbitrarily chosen)
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* 25% of the max.
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*/
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min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
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if (min != dev_priv->vbt.backlight.min_brightness) {
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DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
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dev_priv->vbt.backlight.min_brightness, min);
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}
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/* vbt value is a coefficient in range [0..255] */
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return scale(dev_priv->vbt.backlight.min_brightness, 0, 255,
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0, panel->backlight.max);
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return scale(min, 0, 255, 0, panel->backlight.max);
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}
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static int bdw_setup_backlight(struct intel_connector *connector)
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@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
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/* init the CE partitions. CE only used for gfx on CIK */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
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radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0x8000);
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radeon_ring_write(ring, 0x8000);
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/* setup clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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gpu_addr = rdev->wb.gpu_addr + index;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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rdev->wb.wb[index/4] = cpu_to_le32(tmp);
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr);
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ib.ptr[3] = 1;
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ib.ptr[4] = 0xDEADBEEF;
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ib.length_dw = 5;
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@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -2345,6 +2345,9 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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@ -2552,6 +2555,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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@ -3207,6 +3207,9 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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uint32_t pixel_bytes1 = 0;
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uint32_t pixel_bytes2 = 0;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled) {
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@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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gpu_addr = rdev->wb.gpu_addr + index;
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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}
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ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
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ib.ptr[3] = 0xDEADBEEF;
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ib.length_dw = 4;
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@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -879,6 +879,9 @@ void rs600_bandwidth_update(struct radeon_device *rdev)
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u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
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/* FIXME: implement full support */
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -579,6 +579,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
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u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
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u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -1277,6 +1277,9 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
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struct drm_display_mode *mode0 = NULL;
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struct drm_display_mode *mode1 = NULL;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -2384,6 +2384,9 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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