Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
Nothing too exciting, mostly fixes for ancient boards, but a pretty important fix for DP on some systems. Thanks, * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: fix TTM_PL_TT memtype on pre-nv50 drm/nv50/disp: use correct register to determine DP display bpp drm/nouveau/fb: use correct ram oclass for nv1a hardware drm/nv50/gr: add missing nv_error parameter priv drm/nouveau: fix ENG_RUNLIST register address drm/nv4c/bios: disallow retrieving from prom on nv4x igp's drm/nv4c/vga: decode register is in a different place on nv4x igp's drm/nv4c/mc: nv4x igp's have a different msi rearm register drm/nouveau: set irq_enabled manually
This commit is contained in:
commit
c2288d4d38
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@ -141,6 +141,7 @@ nouveau-y += core/subdev/mc/base.o
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nouveau-y += core/subdev/mc/nv04.o
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nouveau-y += core/subdev/mc/nv40.o
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nouveau-y += core/subdev/mc/nv44.o
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nouveau-y += core/subdev/mc/nv4c.o
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nouveau-y += core/subdev/mc/nv50.o
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nouveau-y += core/subdev/mc/nv94.o
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nouveau-y += core/subdev/mc/nv98.o
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@ -311,7 +311,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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@ -334,7 +334,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
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@ -357,7 +357,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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@ -380,7 +380,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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@ -403,7 +403,7 @@ nv40_identify(struct nouveau_device *device)
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
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device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
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@ -1142,7 +1142,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
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if (conf != ~0) {
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if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
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u32 soff = (ffs(outp.or) - 1) * 0x08;
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u32 ctrl = nv_rd32(priv, 0x610798 + soff);
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u32 ctrl = nv_rd32(priv, 0x610794 + soff);
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u32 datarate;
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switch ((ctrl & 0x000f0000) >> 16) {
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@ -112,7 +112,7 @@ nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine)
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nv_wr32(priv, 0x002270, cur->addr >> 12);
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nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
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if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
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if (!nv_wait(priv, 0x002284 + (engine * 8), 0x00100000, 0x00000000))
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nv_error(priv, "runlist %d update timeout\n", engine);
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mutex_unlock(&nv_subdev(priv)->mutex);
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}
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@ -539,7 +539,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
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ustatus &= ~0x04030000;
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}
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if (ustatus && display) {
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nv_error("%s - TP%d:", name, i);
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nv_error(priv, "%s - TP%d:", name, i);
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nouveau_bitfield_print(nv50_mpc_traps, ustatus);
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pr_cont("\n");
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ustatus = 0;
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@ -47,6 +47,7 @@ struct nouveau_mc_oclass {
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extern struct nouveau_oclass *nv04_mc_oclass;
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extern struct nouveau_oclass *nv40_mc_oclass;
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extern struct nouveau_oclass *nv44_mc_oclass;
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extern struct nouveau_oclass *nv4c_mc_oclass;
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extern struct nouveau_oclass *nv50_mc_oclass;
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extern struct nouveau_oclass *nv94_mc_oclass;
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extern struct nouveau_oclass *nv98_mc_oclass;
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@ -130,6 +130,10 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
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u16 pcir;
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int i;
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/* there is no prom on nv4x IGP's */
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if (device->card_type == NV_40 && device->chipset >= 0x4c)
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return;
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/* enable access to rom */
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if (device->card_type >= NV_50)
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pcireg = 0x088050;
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@ -36,7 +36,7 @@ nv1a_fb_oclass = &(struct nv04_fb_impl) {
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.fini = _nouveau_fb_fini,
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},
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.base.memtype = nv04_fb_memtype_valid,
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.base.ram = &nv10_ram_oclass,
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.base.ram = &nv1a_ram_oclass,
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.tile.regions = 8,
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.tile.init = nv10_fb_tile_init,
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.tile.fini = nv10_fb_tile_fini,
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@ -14,6 +14,7 @@ int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *,
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extern const struct nouveau_mc_intr nv04_mc_intr[];
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int nv04_mc_init(struct nouveau_object *);
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void nv40_mc_msi_rearm(struct nouveau_mc *);
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int nv44_mc_init(struct nouveau_object *object);
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int nv50_mc_init(struct nouveau_object *);
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extern const struct nouveau_mc_intr nv50_mc_intr[];
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extern const struct nouveau_mc_intr nvc0_mc_intr[];
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@ -24,7 +24,7 @@
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#include "nv04.h"
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static int
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int
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nv44_mc_init(struct nouveau_object *object)
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{
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struct nv04_mc_priv *priv = (void *)object;
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45
drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
Normal file
45
drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
Normal file
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@ -0,0 +1,45 @@
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/*
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* Copyright 2014 Ilia Mirkin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ilia Mirkin
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*/
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#include "nv04.h"
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static void
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nv4c_mc_msi_rearm(struct nouveau_mc *pmc)
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{
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struct nv04_mc_priv *priv = (void *)pmc;
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nv_wr08(priv, 0x088050, 0xff);
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}
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struct nouveau_oclass *
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nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
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.base.handle = NV_SUBDEV(MC, 0x4c),
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.base.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv04_mc_ctor,
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.dtor = _nouveau_mc_dtor,
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.init = nv44_mc_init,
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.fini = _nouveau_mc_fini,
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},
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.intr = nv04_mc_intr,
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.msi_rearm = nv4c_mc_msi_rearm,
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}.base;
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@ -1249,7 +1249,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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mem->bus.is_iomem = !dev->agp->cant_use_aperture;
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}
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#endif
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if (!node->memtype)
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if (nv_device(drm->device)->card_type < NV_50 || !node->memtype)
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/* untiled */
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break;
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/* fallthrough, tiled memory */
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@ -376,6 +376,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
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if (ret)
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goto fail_device;
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dev->irq_enabled = true;
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/* workaround an odd issue on nvc1 by disabling the device's
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* nosnoop capability. hopefully won't cause issues until a
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* better fix is found - assuming there is one...
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@ -475,6 +477,7 @@ nouveau_drm_remove(struct pci_dev *pdev)
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_object *device;
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dev->irq_enabled = false;
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device = drm->client.base.device;
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drm_put_dev(dev);
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@ -14,7 +14,9 @@ nouveau_vga_set_decode(void *priv, bool state)
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{
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struct nouveau_device *device = nouveau_dev(priv);
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if (device->chipset >= 0x40)
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if (device->card_type == NV_40 && device->chipset >= 0x4c)
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nv_wr32(device, 0x088060, state);
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else if (device->chipset >= 0x40)
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nv_wr32(device, 0x088054, state);
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else
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nv_wr32(device, 0x001854, state);
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