MLK-18362-3 arm64: dts: add mipi csi camera support on imx8mm-evk
add node for MIPI CSI, CSI, and camera OV5640 Signed-off-by: Robby Cai <robby.cai@nxp.com>pull/10/head
parent
0e9049979e
commit
c273f30b4f
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@ -124,6 +124,19 @@
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pinctrl-names = "default";
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imx8mm-evk {
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pinctrl_csi_pwn: csi_pwn_grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
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>;
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};
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pinctrl_csi_rst: csi_rst_grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
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MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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@ -412,6 +425,16 @@
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};
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};
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&csi1_bridge {
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fsl,mipi-mode;
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status = "okay";
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port {
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csi1_ep: endpoint {
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remote-endpoint = <&csi1_mipi_ep>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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@ -613,6 +636,26 @@
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};
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};
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&mipi_csi_1 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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port {
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mipi1_sensor_ep: endpoint1 {
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remote-endpoint = <&ov5640_mipi1_ep>;
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data-lanes = <2>;
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csis-hs-settle = <13>;
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csis-clk-settle = <2>;
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csis-wclk;
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};
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csi1_mipi_ep: endpoint2 {
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remote-endpoint = <&csi1_ep>;
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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@ -647,6 +690,29 @@
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reg = <0x11>;
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ak4497,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
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};
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ov5640_mipi: ov5640_mipi@3c {
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compatible = "ovti,ov5640_mipi";
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reg = <0x3c>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
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clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
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clock-names = "csi_mclk";
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assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
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<&clk IMX8MM_CLK_CLKO1_DIV>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_200M>;
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assigned-clock-rates = <0>, <25000000>;
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csi_id = <0>;
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pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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mclk = <25000000>;
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mclk_source = <0>;
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port {
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ov5640_mipi1_ep: endpoint {
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remote-endpoint = <&mipi1_sensor_ep>;
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};
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};
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};
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};
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&mu {
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@ -166,6 +166,29 @@
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};
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};
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csi1_bridge: csi1_bridge@32e20000 {
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compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
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reg = <0x0 0x32e20000 0x0 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_CSI1_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>;
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clock-names = "disp-axi", "csi_mclk", "disp_dcic";
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status = "disabled";
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};
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mipi_csi_1: mipi_csi@32e30000 {
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compatible = "fsl,imx8mm-mipi-csi";
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reg = <0x0 0x32e30000 0x0 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MM_CLK_CSI1_CORE_DIV>,
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<&clk IMX8MM_CLK_CSI1_PHY_REF_DIV>;
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clock-names = "mipi_clk", "phy_clk";
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bus-width = <4>;
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status = "disabled";
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};
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mipi_pd: gpc_power_domain@0 {
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compatible = "fsl,imx8mm-pm-domain";
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#power-domain-cells = <0>;
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