clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock is needed by USB 3.0. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
This commit is contained in:
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29859d9315
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cdb2bab78a
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@ -1,4 +1,4 @@
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obj-y += clk-mtk.o clk-pll.o clk-gate.o
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obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-y += clk-mt8135.o
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obj-y += clk-mt8135.o
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obj-y += clk-mt8173.o
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obj-y += clk-mt8173.o
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107
drivers/clk/mediatek/clk-apmixed.c
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107
drivers/clk/mediatek/clk-apmixed.c
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@ -0,0 +1,107 @@
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "clk-mtk.h"
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#define REF2USB_TX_EN BIT(0)
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#define REF2USB_TX_LPF_EN BIT(1)
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#define REF2USB_TX_OUT_EN BIT(2)
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#define REF2USB_EN_MASK (REF2USB_TX_EN | REF2USB_TX_LPF_EN | \
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REF2USB_TX_OUT_EN)
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struct mtk_ref2usb_tx {
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struct clk_hw hw;
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void __iomem *base_addr;
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};
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static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_ref2usb_tx, hw);
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}
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static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw)
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{
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struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
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return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK;
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}
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static int mtk_ref2usb_tx_prepare(struct clk_hw *hw)
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{
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struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
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u32 val;
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val = readl(tx->base_addr);
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val |= REF2USB_TX_EN;
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writel(val, tx->base_addr);
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udelay(100);
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val |= REF2USB_TX_LPF_EN;
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writel(val, tx->base_addr);
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val |= REF2USB_TX_OUT_EN;
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writel(val, tx->base_addr);
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return 0;
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}
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static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw)
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{
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struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
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u32 val;
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val = readl(tx->base_addr);
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val &= ~REF2USB_EN_MASK;
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writel(val, tx->base_addr);
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}
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static const struct clk_ops mtk_ref2usb_tx_ops = {
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.is_prepared = mtk_ref2usb_tx_is_prepared,
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.prepare = mtk_ref2usb_tx_prepare,
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.unprepare = mtk_ref2usb_tx_unprepare,
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};
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struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
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const char *parent_name, void __iomem *reg)
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{
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struct mtk_ref2usb_tx *tx;
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struct clk_init_data init = {};
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struct clk *clk;
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tx = kzalloc(sizeof(*tx), GFP_KERNEL);
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if (!tx)
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return ERR_PTR(-ENOMEM);
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tx->base_addr = reg;
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tx->hw.init = &init;
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init.name = name;
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init.ops = &mtk_ref2usb_tx_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(NULL, &tx->hw);
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if (IS_ERR(clk)) {
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pr_err("Failed to register clk %s: %ld\n", name, PTR_ERR(clk));
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kfree(tx);
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}
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return clk;
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}
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@ -982,6 +982,24 @@ static void __init mtk_pericfg_init(struct device_node *node)
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}
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}
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CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
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CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
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struct mtk_clk_usb {
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int id;
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const char *name;
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const char *parent;
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u32 reg_ofs;
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};
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#define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \
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.id = _id, \
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.name = _name, \
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.parent = _parent, \
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.reg_ofs = _reg_ofs, \
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}
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static const struct mtk_clk_usb apmixed_usb[] __initconst = {
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APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
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};
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#define MT8173_PLL_FMAX (3000UL * MHZ)
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#define MT8173_PLL_FMAX (3000UL * MHZ)
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#define CON0_MT8173_RST_BAR BIT(24)
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#define CON0_MT8173_RST_BAR BIT(24)
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@ -1042,6 +1060,15 @@ static const struct mtk_pll_data plls[] = {
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static void __init mtk_apmixedsys_init(struct device_node *node)
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static void __init mtk_apmixedsys_init(struct device_node *node)
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{
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{
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struct clk_onecell_data *clk_data;
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struct clk_onecell_data *clk_data;
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void __iomem *base;
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struct clk *clk;
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int r, i;
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s(): ioremap failed\n", __func__);
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return;
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}
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mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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if (!clk_data)
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@ -1049,6 +1076,26 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
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const struct mtk_clk_usb *cku = &apmixed_usb[i];
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clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
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base + cku->reg_ofs);
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if (IS_ERR(clk)) {
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pr_err("Failed to register clk %s: %ld\n", cku->name,
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PTR_ERR(clk));
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continue;
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}
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clk_data->clks[cku->id] = clk;
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}
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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mtk_clk_enable_critical();
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mtk_clk_enable_critical();
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}
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}
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CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
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CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
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@ -180,6 +180,9 @@ void mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_onecell_data *clk_data);
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struct clk_onecell_data *clk_data);
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struct clk *mtk_clk_register_ref2usb_tx(const char *name,
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const char *parent_name, void __iomem *reg);
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#ifdef CONFIG_RESET_CONTROLLER
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#ifdef CONFIG_RESET_CONTROLLER
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void mtk_register_reset_controller(struct device_node *np,
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void mtk_register_reset_controller(struct device_node *np,
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unsigned int num_regs, int regofs);
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unsigned int num_regs, int regofs);
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@ -317,7 +317,7 @@ void __init mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
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const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
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{
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{
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void __iomem *base;
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void __iomem *base;
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int r, i;
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int i;
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struct clk *clk;
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struct clk *clk;
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base = of_iomap(node, 0);
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base = of_iomap(node, 0);
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@ -339,9 +339,4 @@ void __init mtk_clk_register_plls(struct device_node *node,
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clk_data->clks[pll->id] = clk;
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clk_data->clks[pll->id] = clk;
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}
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}
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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}
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@ -175,7 +175,8 @@
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#define CLK_APMIXED_APLL2 12
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#define CLK_APMIXED_APLL2 12
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#define CLK_APMIXED_LVDSPLL 13
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#define CLK_APMIXED_LVDSPLL 13
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#define CLK_APMIXED_MSDCPLL2 14
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#define CLK_APMIXED_MSDCPLL2 14
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#define CLK_APMIXED_NR_CLK 15
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#define CLK_APMIXED_REF2USB_TX 15
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#define CLK_APMIXED_NR_CLK 16
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/* INFRA_SYS */
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/* INFRA_SYS */
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