xtensa: add alternative kernel memory layouts
MMUv3 is able to support low memory bigger than 128MB. Implement 256MB and 512MB KSEG layouts: - add Kconfig selector for KSEG layout; - add KSEG base address, size and alignment definitions to arch/xtensa/include/asm/kmem_layout.h; - use new definitions in TLB initialization; - add build time memory map consistency checks. See Documentation/xtensa/mmu.txt for the details of new memory layouts. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -62,3 +62,127 @@ limitations apply:
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6. The IO area covers the entire 256MB segment of parent-bus-address; the
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"ranges" triplet length field is ignored
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MMUv3 address space layouts.
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============================
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Default MMUv2-compatible layout.
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Symbol VADDR Size
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+------------------+
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| Userspace | 0x00000000 TASK_SIZE
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+------------------+ 0x40000000
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+------------------+
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| Page table | 0x80000000
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+------------------+ 0x80400000
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+------------------+
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| KMAP area | PKMAP_BASE PTRS_PER_PTE *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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| | (4MB * DCACHE_N_COLORS)
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+------------------+
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
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| | NR_CPUS *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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+------------------+ FIXADDR_TOP 0xbffff000
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+------------------+
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| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
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+------------------+ VMALLOC_END
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| Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
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| remap area 1 |
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+------------------+
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
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| remap area 2 |
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+------------------+
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+------------------+
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
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+------------------+
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
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+------------------+
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
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+------------------+
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
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+------------------+
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256MB cached + 256MB uncached layout.
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Symbol VADDR Size
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+------------------+
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| Userspace | 0x00000000 TASK_SIZE
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+------------------+ 0x40000000
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+------------------+
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| Page table | 0x80000000
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+------------------+ 0x80400000
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+------------------+
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| KMAP area | PKMAP_BASE PTRS_PER_PTE *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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| | (4MB * DCACHE_N_COLORS)
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+------------------+
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
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| | NR_CPUS *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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+------------------+ FIXADDR_TOP 0x9ffff000
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+------------------+
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| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
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+------------------+ VMALLOC_END
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| Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
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| remap area 1 |
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+------------------+
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
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| remap area 2 |
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+------------------+
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+------------------+
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
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+------------------+
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
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+------------------+
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+------------------+
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
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+------------------+
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
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+------------------+
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512MB cached + 512MB uncached layout.
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Symbol VADDR Size
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+------------------+
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| Userspace | 0x00000000 TASK_SIZE
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+------------------+ 0x40000000
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+------------------+
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| Page table | 0x80000000
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+------------------+ 0x80400000
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+------------------+
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| KMAP area | PKMAP_BASE PTRS_PER_PTE *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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| | (4MB * DCACHE_N_COLORS)
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+------------------+
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| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
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| | NR_CPUS *
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| | DCACHE_N_COLORS *
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| | PAGE_SIZE
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+------------------+ FIXADDR_TOP 0x8ffff000
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+------------------+
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| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
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+------------------+ VMALLOC_END
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| Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
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| remap area 1 |
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+------------------+
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| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
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| remap area 2 |
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+------------------+
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+------------------+
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| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
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+------------------+
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| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
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+------------------+
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| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
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+------------------+
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| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
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+------------------+
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@ -236,6 +236,50 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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If in doubt, say Y.
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config KSEG_PADDR
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hex "Physical address of the KSEG mapping"
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depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
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default 0x00000000
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help
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This is the physical address where KSEG is mapped. Please refer to
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the chosen KSEG layout help for the required address alignment.
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Unpacked kernel image (including vectors) must be located completely
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within KSEG.
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Physical memory below this address is not available to linux.
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If unsure, leave the default value here.
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choice
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prompt "KSEG layout"
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depends on MMU
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default XTENSA_KSEG_MMU_V2
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config XTENSA_KSEG_MMU_V2
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bool "MMUv2: 128MB cached + 128MB uncached"
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help
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MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
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at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
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without cache.
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KSEG_PADDR must be aligned to 128MB.
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config XTENSA_KSEG_256M
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bool "256MB cached + 256MB uncached"
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depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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help
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TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
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with cache and to 0xc0000000 without cache.
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KSEG_PADDR must be aligned to 256MB.
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config XTENSA_KSEG_512M
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bool "512MB cached + 512MB uncached"
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depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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help
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TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
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with cache and to 0xc0000000 without cache.
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KSEG_PADDR must be aligned to 256MB.
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endchoice
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config HIGHMEM
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bool "High Memory Support"
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depends on MMU
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@ -59,6 +59,11 @@ enum fixed_addresses {
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*/
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static __always_inline unsigned long fix_to_virt(const unsigned int idx)
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{
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/* Check if this memory layout is broken because fixmap overlaps page
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* table.
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*/
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BUILD_BUG_ON(FIXADDR_START <
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XCHAL_PAGE_TABLE_VADDR + XCHAL_PAGE_TABLE_SIZE);
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BUILD_BUG_ON(idx >= __end_of_fixed_addresses);
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return __fix_to_virt(idx);
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}
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@ -68,6 +68,11 @@ void kunmap_high(struct page *page);
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static inline void *kmap(struct page *page)
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{
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/* Check if this memory layout is broken because PKMAP overlaps
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* page table.
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*/
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BUILD_BUG_ON(PKMAP_BASE <
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XCHAL_PAGE_TABLE_VADDR + XCHAL_PAGE_TABLE_SIZE);
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BUG_ON(in_interrupt());
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if (!PageHighMem(page))
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return page_address(page);
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@ -116,22 +116,35 @@
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add a5, a5, a4
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bne a5, a2, 3b
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/* Step 4: Setup MMU with the old V2 mappings. */
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/* Step 4: Setup MMU with the requested static mappings. */
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movi a6, 0x01000000
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wsr a6, ITLBCFG
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wsr a6, DTLBCFG
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isync
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movi a5, 0xd0000005
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movi a4, CA_WRITEBACK
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movi a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY
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movi a4, XCHAL_KSEG_PADDR + CA_WRITEBACK
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wdtlb a4, a5
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witlb a4, a5
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movi a5, 0xd8000005
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movi a4, CA_BYPASS
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movi a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY
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movi a4, XCHAL_KSEG_PADDR + CA_BYPASS
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wdtlb a4, a5
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witlb a4, a5
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#ifdef CONFIG_XTENSA_KSEG_512M
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movi a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
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movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK
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wdtlb a4, a5
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witlb a4, a5
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movi a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
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movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS
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wdtlb a4, a5
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witlb a4, a5
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#endif
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movi a5, XCHAL_KIO_CACHED_VADDR + 6
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movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
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wdtlb a4, a5
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@ -13,13 +13,59 @@
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#include <asm/types.h>
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#ifdef CONFIG_MMU
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/*
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* Fixed TLB translations in the processor.
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*/
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#define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
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#define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
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#if defined(CONFIG_XTENSA_KSEG_MMU_V2)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
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#define XCHAL_KSEG_TLB_WAY 5
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#elif defined(CONFIG_XTENSA_KSEG_256M)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_TLB_WAY 6
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#elif defined(CONFIG_XTENSA_KSEG_512M)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_TLB_WAY 6
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#else
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#error Unsupported KSEG configuration
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#endif
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#ifdef CONFIG_KSEG_PADDR
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#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR)
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#else
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#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000)
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#endif
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#if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1)
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#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
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#endif
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#else
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
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#endif
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#endif
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@ -27,10 +27,12 @@
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#ifdef CONFIG_MMU
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#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
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#define MAX_MEM_PFN XCHAL_KSEG_SIZE
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#define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \
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PHYS_PFN(XCHAL_KSEG_SIZE))
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#else
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#define PAGE_OFFSET __XTENSA_UL_CONST(0)
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#define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
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#define MAX_LOW_PFN (PHYS_PFN(PLATFORM_DEFAULT_MEM_START) + \
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PHYS_PFN(PLATFORM_DEFAULT_MEM_SIZE))
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#endif
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#define PGTABLE_START 0x80000000
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@ -18,7 +18,8 @@
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# define __XTENSA_UL_CONST(x) x
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#else
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# define __XTENSA_UL(x) ((unsigned long)(x))
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# define __XTENSA_UL_CONST(x) x##UL
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# define ___XTENSA_UL_CONST(x) x##UL
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# define __XTENSA_UL_CONST(x) ___XTENSA_UL_CONST(x)
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#endif
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#ifndef __ASSEMBLY__
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@ -266,8 +266,7 @@ void __init bootmem_init(void)
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if (min_low_pfn > max_pfn)
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panic("No memory found!\n");
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max_low_pfn = max_pfn < MAX_MEM_PFN >> PAGE_SHIFT ?
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max_pfn : MAX_MEM_PFN >> PAGE_SHIFT;
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max_low_pfn = min(max_pfn, MAX_LOW_PFN);
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/* Find an area to use for the bootmem bitmap. */
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