tg3: Add TG3_FLG3_USE_PHYLIB
This patch introduces the TG3_FLG3_USE_PHYLIB flag and applies it to some select places. This work makes later patches a little easier to read. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1605,7 +1605,7 @@ static void tg3_power_down_phy(struct tg3 *tp)
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tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
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udelay(40);
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return;
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} else {
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} else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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@ -1687,18 +1687,22 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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tw32(TG3PCI_MISC_HOST_CTRL,
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misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
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if (tp->link_config.phy_is_low_power == 0) {
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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tp->link_config.phy_is_low_power = 1;
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tp->link_config.orig_speed = tp->link_config.speed;
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tp->link_config.orig_duplex = tp->link_config.duplex;
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tp->link_config.orig_autoneg = tp->link_config.autoneg;
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}
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} else {
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if (tp->link_config.phy_is_low_power == 0) {
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tp->link_config.phy_is_low_power = 1;
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tp->link_config.orig_speed = tp->link_config.speed;
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tp->link_config.orig_duplex = tp->link_config.duplex;
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tp->link_config.orig_autoneg = tp->link_config.autoneg;
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
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tp->link_config.speed = SPEED_10;
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tp->link_config.duplex = DUPLEX_HALF;
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tp->link_config.autoneg = AUTONEG_ENABLE;
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tg3_setup_phy(tp, 0);
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if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
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tp->link_config.speed = SPEED_10;
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tp->link_config.duplex = DUPLEX_HALF;
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tp->link_config.autoneg = AUTONEG_ENABLE;
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tg3_setup_phy(tp, 0);
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}
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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@ -1729,8 +1733,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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u32 mac_mode;
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
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udelay(40);
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if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
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udelay(40);
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}
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if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
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mac_mode = MAC_MODE_PORT_MODE_GMII;
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@ -3821,7 +3827,15 @@ static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
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sblk->status = SD_STATUS_UPDATED |
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(sblk->status & ~SD_STATUS_LINK_CHG);
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spin_lock(&tp->lock);
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tg3_setup_phy(tp, 0);
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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tw32_f(MAC_STATUS,
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(MAC_STATUS_SYNC_CHANGED |
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MAC_STATUS_CFG_CHANGED |
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MAC_STATUS_MI_COMPLETION |
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MAC_STATUS_LNKSTATE_CHANGED));
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udelay(40);
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} else
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tg3_setup_phy(tp, 0);
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spin_unlock(&tp->lock);
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}
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}
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@ -6602,7 +6616,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tg3_abort_hw(tp, 1);
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}
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if (reset_phy)
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if (reset_phy &&
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!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
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tg3_phy_reset(tp);
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err = tg3_chip_reset(tp);
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@ -7153,13 +7168,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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udelay(10);
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if (tp->link_config.phy_is_low_power) {
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tp->link_config.phy_is_low_power = 0;
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tp->link_config.speed = tp->link_config.orig_speed;
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tp->link_config.duplex = tp->link_config.orig_duplex;
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tp->link_config.autoneg = tp->link_config.orig_autoneg;
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}
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tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
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tw32_f(MAC_MI_MODE, tp->mi_mode);
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udelay(80);
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@ -7210,19 +7218,28 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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}
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err = tg3_setup_phy(tp, 0);
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if (err)
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return err;
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if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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if (tp->link_config.phy_is_low_power) {
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tp->link_config.phy_is_low_power = 0;
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tp->link_config.speed = tp->link_config.orig_speed;
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tp->link_config.duplex = tp->link_config.orig_duplex;
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tp->link_config.autoneg = tp->link_config.orig_autoneg;
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
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u32 tmp;
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err = tg3_setup_phy(tp, 0);
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if (err)
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return err;
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/* Clear CRC stats. */
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if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
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tg3_writephy(tp, MII_TG3_TEST1,
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tmp | MII_TG3_TEST1_CRC_EN);
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tg3_readphy(tp, 0x14, &tmp);
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
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u32 tmp;
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/* Clear CRC stats. */
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if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
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tg3_writephy(tp, MII_TG3_TEST1,
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tmp | MII_TG3_TEST1_CRC_EN);
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tg3_readphy(tp, 0x14, &tmp);
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}
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}
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}
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@ -9644,7 +9661,8 @@ static int tg3_test_loopback(struct tg3 *tp)
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tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
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!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
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if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
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err |= TG3_PHY_LOOPBACK_FAILED;
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}
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@ -2480,6 +2480,7 @@ struct tg3 {
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#define TG3_FLG3_ENABLE_APE 0x00000002
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#define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
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#define TG3_FLG3_5701_DMA_BUG 0x00000008
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#define TG3_FLG3_USE_PHYLIB 0x00000010
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struct timer_list timer;
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u16 timer_counter;
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