clk: samsung: exynos4: Add divider clock id for memory bus frequency
This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
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/* list of divider clocks supported in all exynos4 soc's */
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/* list of divider clocks supported in all exynos4 soc's */
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static struct samsung_div_clock exynos4_div_clks[] __initdata = {
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static struct samsung_div_clock exynos4_div_clks[] __initdata = {
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DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
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DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
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DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
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DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
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DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
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DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
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CLKOUT_CMU_LEFTBUS, 8, 6),
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CLKOUT_CMU_LEFTBUS, 8, 6),
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DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
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DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
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DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
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DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
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DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
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DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
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CLKOUT_CMU_RIGHTBUS, 8, 6),
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CLKOUT_CMU_RIGHTBUS, 8, 6),
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@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
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CLK_SET_RATE_PARENT, 0),
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CLK_SET_RATE_PARENT, 0),
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DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
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DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
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DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
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DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
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DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
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DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
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DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
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DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
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DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
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DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
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DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
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DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
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DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
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DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
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DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
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DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
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@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
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DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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};
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};
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@ -262,8 +262,13 @@
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#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
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#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
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#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
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#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
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#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
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#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
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#define CLK_DIV_ACP 456
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#define CLK_DIV_DMC 457
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#define CLK_DIV_C2C 458 /* Exynos4x12 only */
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#define CLK_DIV_GDL 459
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#define CLK_DIV_GDR 460
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/* must be greater than maximal clock id */
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 456
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#define CLK_NR_CLKS 461
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
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