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MLK-16530-3 rpmsg: imx: init mu and limit the pingpong cycles 

- Init mu power and clk.
- Change the cycles of the pingpong demot refer to
the limitation of M4 side.
When the received data larger than 100, the
pingpong of M4 side would be finished.
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
pull/10/head
Richard Zhu 2017-09-21 16:46:26 +08:00 committed by Jason Liu
parent c91cf3ce43
commit e9d2a097c7
2 changed files with 10 additions and 21 deletions
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29
drivers/rpmsg/imx_rpmsg.c
View File

@ -467,7 +467,7 @@ static int imx_rpmsg_probe(struct platform_device *pdev)
return ret;
}
if (variant == IMX7D) {
if (variant == IMX7D || variant == IMX8QXP) {
clk = of_clk_get(np_mu, 0);
if (IS_ERR(clk)) {
pr_err("mu clock source missing or invalid\n");
@ -481,27 +481,16 @@ static int imx_rpmsg_probe(struct platform_device *pdev)
}
INIT_DELAYED_WORK(&rpmsg_work, rpmsg_work_handler);
if (variant == IMX8QXP) {
/*
* MU0_A0 of M4 side is used as RPMSG MU.
* And it would be initialized by M4 before
* A cores are booted up.
*/
MU_Init(mu_base);
/*
* bit26 is used by rpmsg channels.
* bit0 of MX7ULP_MU_CR used to let m4 to know MU is ready now
*/
MU_Init(mu_base);
if (variant == IMX7ULP) {
MU_EnableRxFullInt(mu_base, 1);
pr_info("MU has been initalized by M4!\n");
MU_SetFn(mu_base, 1);
} else {
/*
* bit26 is used by rpmsg channels.
* bit0 of MX7ULP_MU_CR used to let m4 to know MU is ready now
*/
MU_Init(mu_base);
if (variant == IMX7ULP) {
MU_EnableRxFullInt(mu_base, 1);
MU_SetFn(mu_base, 1);
} else {
MU_EnableRxFullInt(mu_base, 1);
}
MU_EnableRxFullInt(mu_base, 1);
}
BLOCKING_INIT_NOTIFIER_HEAD(&(mu_rpmsg_box.notifier));

2
drivers/rpmsg/imx_rpmsg_pingpong.c
View File

@ -18,7 +18,7 @@
#include <linux/rpmsg.h>
#define MSG "hello world!"
#define MSG_LIMIT 100000
#define MSG_LIMIT 51
static unsigned int rpmsg_pingpong;
static int rx_count;