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7 Commits (1076fe28af4fb6cdd93a2b82247b36ce26180150)

Author SHA1 Message Date
Masahiro Yamada c488c2e141 clk: uniphier: fix DAPLL2 clock rate of Pro5
[ Upstream commit 67affb78a4 ]

The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-12-14 09:28:24 +01:00
Masahiro Yamada 5c6201e60a clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs
I made a mistake as for naming for this block.  The MIO block is not
implemented for these 3 SoCs in the first place.  The current naming
will be a trouble if an SoC with both MIO and SD-ctrl blocks appear
in the future.

This driver has just been merged in the previous merge window.
Rename it before the release.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19 13:15:05 -07:00
Masahiro Yamada 7d36b9c102 clk: uniphier: fix memory overrun bug
The first loop of this "for" statement writes memory beyond the
allocated clk_hw_onecell_data.

It should be:
    for (clk_num--; clk_num >= 0; clk_num--)
            ...

Or more simply:
    while (--clk_num >= 0)
            ...

Fixes: 734d82f4a6 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-19 13:14:18 -07:00
Masahiro Yamada c0ce317f0c clk: uniphier: fix type of variable passed to regmap_read()
The 3rd argument of regmap_read() takes a pointer to unsigned int.
This driver is saved just because u32 happens to be typedef'ed as
unsigned int, but we should not rely on that fact.  Change the
variable type just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17 15:20:52 -07:00
Masahiro Yamada 8236d9ac4c clk: uniphier: add system clock support for sLD3 SoC
I do not know why, but I missed to add this compatible string in
the initial commit of this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17 15:20:50 -07:00
Masahiro Yamada 7f4d3b52b6 clk: uniphier: add clock data for UniPhier SoCs
Add clock data arrays for all UniPhier SoCs with a binding document.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:31:38 -07:00
Masahiro Yamada 734d82f4a6 clk: uniphier: add core support code for UniPhier clock driver
This includes UniPhier clock driver code, except SoC-specific
data arrays.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:31:33 -07:00