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31 Commits (9e8cb59e91afd28102e973332a7ddebaa1416f62)

Author SHA1 Message Date
Sandor Yu 9e8cb59e91 MLK-20518: hdp: Fix memory out of bounds access
Fix memory out of bounds access.
Change arry type for functopn avi info frame,
Align the arry type and its length.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 2fc41a88c9da514ae3f377e7cb73f4df886f038e)
2018-12-05 14:57:58 +08:00
Sandor Yu dfd24b052e MLK-20415: drm: imx: hdp: Adjust HDMI Vswing
The iMX8QM HDMI voltage swing needs to be increased for HDMI compliance.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 5ba997eef35fc74653c29bb99dbe4d97292dc6e4)
2018-11-20 10:50:36 +08:00
Oliver Brown 81c7646749 MLK-20332 drm: imx hdp: Display version information for HDMI/DP firmware
The HDMI/DP firmware verison will now be displayed.
Moved firmware handling to common file for HDMI and DisplayPort.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-11-13 08:56:23 -06:00
Laurentiu Palcu 31d0619322 MLK-20304-1 drm/imx/hdp: add mode_fixup hook and better handling of DC and CS
The HDMI sink may support different color depths for RGB and/or YUV
colorspaces. Currently, for mscale, 10-bit YUV420 is used only for
2160p@60. For the rest of modes 8-bit RGB is used.

This patch will add a mode_fixup() hook in the hdp_ops struct, allowing
each platform to perform a better handling of the various color depths
and colorspaces.

With the current patch, the RGB output will always be preferred to YUV
colorspaces, given the same color depth, since YUV colorspaces perform
UV subsampling, producing less quality. Also, whenever possible, better
color depth will be preferred (12-bit, 10-bit and, lastly, 8-bit).

The chosen colorspace and color depth will always be based on EDID's
Capability Map Data Block and YUV420 Video Data Block, as well as on
HDMI controller's known clock constraints.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-11-13 16:11:35 +02:00
Sandor Yu 8eb490182e MLK-19495: hdp: Add vendor infoframe
VIC code check is introduced in 4.14.y,
if a mode is found in HDMI 1.4b 4K modes.
HDMI driver should send its VIC in vendor infoframes.
Add vendor infoframe setting.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu e1ebd3a776 MLK-17795: drm: imx: hdp: Fix 10-bit to 8-bit color depth switch on iMX8MQ
When switching from a 10-bit to an 8-bit color depth, the PHY pixel engine
simply stops functioning correctly 90% of the time. This results in the
HDMI sink not detecting any signal.

This patch will reset the PHY pixel engine after the pipe clocks are ON,
in the bridge enable callback. This will make the pixel engine work
correctly when BPC changes. Resetting the pixel engine before all the pipe
clocks are on, produces no results.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 72246ac9ccfa2074f4f575292af10d19a58c95c4)
2018-10-29 11:10:38 +08:00
Oliver Brown c485aab546 MLK-19310: drm: imx: hdp: Add support for 4K50
4K@50 does not currently work. This patch will enable the scambler for
VIC96@50Hz.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 0f13947a2fb72673b19c9f154eb202a9be916c4f)
2018-10-29 11:10:38 +08:00
Oliver Brown 6dbe6a2efd MLK-18904-7: imx: hdp: Changing Reset function
Reset function parameters are changing to support i.MX8M (MCU2).

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu b794674115 MLK-18726-1: hdmi: Disable GCP when bpp is 24 to pass CTS 7-19
Refer to HDMI 1.4 section 6.5.3, non-zero CD data GCP should send in
deep color mode.
Now, when HDMI work in 24bpp, it will send non-zero CD(0x4 for 24bit)
data GCP to protocol analyzer.
It means current HDMI source is working in “24bit deep color mode”.

But HDMI 1.4 CTS 7-19 required DUT should in “No Deep Color support”.
Protocol analyzer expect received zero CD GCP or no GCP.

Disable GCP when bpp is 24 to pass CTS 7-19.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu f3b1b2d2d6 MLK-18728: drm: imx: hdp: fix 4K@60 on mscale
On mscale, 4K@60 uses YUV420. However, the following commit:

8eeed3553bd1: MLK-18690-1: hdmi: Rewrite hdmi avi infoframe function

moved to using the kernel built-in infoframe creation routine, instead
of Cadence's one, but skipped handling the various colorspace formats.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu bb26ca75ca MLK-18690-1: hdmi: Rewrite hdmi avi infoframe function
Remove Cadence AVI infoframe function.
Replace with hdmi avi infoframe api function.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 35f49c493b MLK-18558-04: hdp: Rename hdmi phy config function
Rename imx8qm hdmi phy config function,
add ss28fdsoi postfix.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu a73ac447d9 MLK-18558-03: hdp: Add hdmi phy config table for imx8m
Add hdmi phy config table for imx8m.
Rebase imx8m hdmi code to CDN_API_1_0_37.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Shengjiu Wang cf85ee55ab MLK-18368-7: imx-hdmi: change the entry id of meta data
For entry id of video is 0,  audio is 1, if entry id of meta data is
1, then it conflict with audio.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
2018-10-29 11:10:38 +08:00
Oliver Brown 70c788660a MLK-17893 drm: imx: hdp: Adjust HDMI Vswing
The HDMI voltage swing needs to be increased for HDMI compliance.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu 2f7a1ab7d7 MLK-17703-3: drm: imx: hdp: send the right colorimetry to the sink
Currently, the colorimetry was hardcoded to NONE. However, a sink may support
different types of colorimetry. This patch will allow for the colorimetry to be
set according to what the sink supports.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Sandor Yu <sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 96627e9729 MLK-17692-4: imx hdp: Add pixel clock return check
Return 0 if pixel clock isn't supported by hdmi phy.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 99ab0e260c MLK-17692-3: imx hdp: Remove CDN vic table
Remove CDN vic table and replace with drm_display_mode.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu d2d38e0763 MLK-17671-2: drm: imx: hdp: mscale: remove delay at the end of mode setting
Since DCSS was moved to use VIDEO2_PLL clock, HDMI phy clock is not used
anymore. Hence, this delay here is not necessary. It's been added inside
DCSS driver.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu 2ccd87278f MLK-17634-14: drm: imx: dcss: Add basic HDR10 support
This patch adds basic HDR10 support. However, full support depends on
subsequent patches.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-10-29 11:10:38 +08:00
Laurentiu Palcu 66e7685cbe MLK-17634-12: drm: imx: hdp: Send HDR metadata to the sink
If the HDR metadata proprety is set, then the metadata will be sent
to the sink at the next mode set.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu d8faf554c4 MLK-17489-3: hdp: use the drm debug log
Use drm debug log function.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 26e6c0d92d MLK-17456-2: hdmi: Remove debug log
Remove debug log

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Oliver Brown ee495e16f2 MLK-17206 hdp: Disable firmware hdp loading
Disabling HDP firmware loading except for debug.
Added simple checks to test HDP firmware status.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu abc8c111e2 MLK-17107-02: hdmi: Add api function return check
Add api function return check to hdmi api call.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit cba6f4fc6f382731fabf938fb9e03db1c17b1666)

Conflicts:
	drivers/gpu/drm/imx/hdp/imx-hdmi.c
2018-10-29 11:10:38 +08:00
Sandor Yu 7008dab06a MLK-17126-4: hdp: Fix V/Hsync polarity issue
Remove v/hsync polarity adjust function.
Add pixel link mux configuration function for imx8qm.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 53db814c9c MLK-17126-2: hdp: Support imx8qm HDMI function
Add phy reset before hdmi/dp phy init.
Reparent hdmi pixel clock to av_pll.
Combine DP and HDMI ipg clock function.
Add DP and HDMI pixel clock set rate function.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 6479efb72f MLK-17003: hdmi: More delay need for hdmi phy init
DRM core waits for 50ms for a vblank interrupt to come
after changing the mode. But in video mode change from
4Kp60 to 480p60 case, the VBLANK interrupt is not coming
in 50ms, drm core driver will dump the followed warning
information.

[ 1034.956833] [CRTC:25] vblank wait timed out
[ 1034.961069] ------------[ cut here ]------------
[ 1034.965702] WARNING: CPU: 0 PID: 3485 at
/home/bamboo/build/4.9.51-8mq-beta/fsl-imx-internal-xwayland/temp_build_dir/build_fsl-imx-internal-xwayland/tmp/work-shared/imx8mqevk/kernel-source/drivers/gpu/drm/drm_atomic_helper.c:1140
drm_atomic_helper_wait_for_vblanks+0x230/0x238
[ 1034.990111] Modules linked in: 8021q garp stp mrp galcore(O) ipv6
[ 1034.996289]
[ 1034.997785] CPU: 0 PID: 3485 Comm: modetest Tainted: G        W  O
4.9.51-imx_4.9.51_imx8m_beta+gaf29127 #1
[ 1035.007783] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 1035.012832] task: ffff8000b6c49900 task.stack: ffff8000b64cc000
[ 1035.018751] PC is at drm_atomic_helper_wait_for_vblanks+0x230/0x238
[ 1035.025016] LR is at drm_atomic_helper_wait_for_vblanks+0x230/0x238
[ 1035.031281] pc : [<ffff0000085a6b08>] lr : [<ffff0000085a6b08>]
pstate: 00000145
[ 1035.038673] sp : ffff8000b64cfa50
[ 1035.041985] x29: ffff8000b64cfa50 x28: 0000000000000000
[ 1035.047316] x27: 0000000000000000 x26: ffff8000b86c4820
[ 1035.052646] x25: 0000000000000090 x24: 0000000000006d57
[ 1035.057976] x23: 0000000000000018 x22: ffff8000b86c3800
[ 1035.063306] x21: ffff8000b955fc00 x20: ffff8000b64f1180
[ 1035.068637] x19: 0000000000000000 x18: 0000000000000010
[ 1035.073967] x17: 0000000000000000 x16: 0000000000000000
[ 1035.079297] x15: 0000000000000006 x14: ffff00008937abc7
[ 1035.084628] x13: ffff00000937abd5 x12: 0000000000000007
[ 1035.089959] x11: 000000000000022f x10: 0000000005f5e0ff
[ 1035.095289] x9 : 0000000000000230 x8 : 6974207469617720
[ 1035.100619] x7 : 6b6e616c6276205d x6 : ffff00000937abf6
[ 1035.105949] x5 : 0000000000000000 x4 : 0000000000000000
[ 1035.111279] x3 : 0000000000000000 x2 : ffff8000b64cc000
[ 1035.116609] x1 : ffff8000b64cc000 x0 : 000000000000001f
[ 1035.121938]
[ 1035.123428] ---[ end trace d3bf25e791b7a9c7 ]---
[ 1035.128043] Call trace:
[ 1035.130488] Exception stack(0xffff8000b64cf880 to 0xffff8000b64cf9b0)
[ 1035.136928] f880: 0000000000000000 0001000000000000 ffff8000b64cfa50
ffff0000085a6b08
[ 1035.144756] f8a0: 0000000000000002 0000000000000004 ffff00000937cfe8
000000000000001f
[ 1035.152584] f8c0: ffff00000937a000 ffff000008f67838 ffff8000b64cf970
ffff0000081009f0
[ 1035.160412] f8e0: 0000000000000000 ffff8000b64f1180 ffff8000b955fc00
ffff8000b86c3800
[ 1035.168240] f900: 0000000000000018 0000000000006d57 0000000000000090
ffff8000b86c4820
[ 1035.176067] f920: 000000000000001f ffff8000b64cc000 ffff8000b64cc000
0000000000000000
[ 1035.183895] f940: 0000000000000000 0000000000000000 ffff00000937abf6
6b6e616c6276205d
[ 1035.191723] f960: 6974207469617720 0000000000000230 0000000005f5e0ff
000000000000022f
[ 1035.199551] f980: 0000000000000007 ffff00000937abd5 ffff00008937abc7
0000000000000006
[ 1035.207377] f9a0: 0000000000000000 0000000000000000
[ 1035.212255] [<ffff0000085a6b08>]
drm_atomic_helper_wait_for_vblanks+0x230/0x238
[ 1035.219562] [<ffff0000085a96a0>]
drm_atomic_helper_commit_tail+0x50/0x68
[ 1035.226261] [<ffff0000085a971c>] commit_tail+0x64/0x80
[ 1035.231398] [<ffff0000085a97f8>] drm_atomic_helper_commit+0xa8/0x108
[ 1035.237752] [<ffff0000085ec468>] dcss_drm_atomic_commit+0x100/0x148
[ 1035.244018] [<ffff0000085c8308>] drm_atomic_commit+0x50/0x60
[ 1035.249676] [<ffff0000085a9d28>]
drm_atomic_helper_set_config+0x88/0xc8
[ 1035.256290] [<ffff0000085bb5f8>]
drm_mode_set_config_internal+0x68/0xf8
[ 1035.262903] [<ffff0000085bc9dc>] drm_mode_setcrtc+0x38c/0x450
[ 1035.268649] [<ffff0000085b3ba8>] drm_ioctl+0x198/0x448
[ 1035.273788] [<ffff0000081f067c>] do_vfs_ioctl+0xa4/0x748
[ 1035.279099] [<ffff0000081f0dac>] SyS_ioctl+0x8c/0xa0
[ 1035.284064] [<ffff000008082f4c>] __sys_trace_return+0x0/0x4

Added more delay for hdmi phy init will fixed the issue.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 235f4eed85 MLK-16946-2: hdmi: Enable cable hotplug detect function
-Enable HDMI/DP cable hotplug detect function.
-Remove HPD polling thread function.
-Move HDMI/DP FW init and download function
before hdmi drm register.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu 95318d7c7b MLK-16748-02: HDMI: Support iMX8MQ HDMI in HDMI DRM driver
-Add iMX8MQ HDMI function support in iMX8 HDMI DRM driver.
-EDID read function supported for iMX8MQ.
-Move iMX8QM clock management functions and pixel link
setting functions to iMX8QM SOC specific struct.
-replace printk with pr_info, dev_warn and dev_err.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
2018-10-29 11:10:38 +08:00
Sandor Yu ccf331b51d MLK-16538-3: hdmi/dp: Add imx8qm hdmi/dp driver
Add hdmi/dp drm architecture driver.
HDMI and DP driver can work in imx8qm ARM2 board.
The driver support basic hotplug function.
Default working mode is 1080p60.

Acked-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
2018-10-29 11:10:38 +08:00