This needs to be one individual change since otherwise the driver
and the dtbs won't build anymore. This updates all the dts and dtsi files,
the clock index defines and the imx8mq clock driver itself
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
No need to enable IMX8MQ_CLK_NAND_USDHC_BUS_CG during the imx8mq clock driver
init, so remove it from the clks_init_on[].
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 6c90e1bfc38eab27921d26b1218993e5cd52a425)
No need to enable IMX8MQ_CLK_AUDIO_AHB_DIV during imx8mq clock
driver init, so remove it from the clks_init_on[].
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit b13900ec3296f579f54581483858cc053d2bbff3)
Add a new init-on-array property, the clk driver will
parse this array and prepare enable the related clocks.
Previously, the clocks needs to be init on are hardcoded in SoC
clk driver. When we need to support two OSes, some clks
needs to be ini on, however such clocks does not need to be init on
for Single Linux OS environment.
At current stage using Jailhouse hypervisor supporting Two Linux OS,
OS1 use SDHC2, OS2 use SDHC0, they share one IMX8MQ_CLK_NAND_USDHC_BUS_CG,
because no power management supported, so we need clk_ignore_unused
and make sure this clk being enabled, to make sure the 2nd OS
could has SDHC0 working.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 9e6e0ffe8876d5f52ee372ec438ab30ef01c4a5d)
External differential clock phy_27m can be set to all
plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid
confusion as clock source is the same option for all plls
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 513eb64189903ca24c7f5ae140703831159b0578)
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
When the system reaches the passive critical trip point, VPU device cooling
need to change the clock rate on the fly. So change the VPU related clocks
flags to make sure the clock rate can be changed successfully.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
reduce the NOC, main AXI and AHB bus clock frequency to save power when DDR enter low
frequency mode. VDDSOC is ~195mA during video play, and ~180mA in idle.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOT
These root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Set the video_pll1 clock's source and rate which are
used for pixel clock and mipi dphy reference clock
source.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Add wdog nodes in dtsi.
Enable wdog1 for imx8mq evk board.
Enable imx wdt in defconfig.
Correct clock, offset 0x4550 is actually for wdog3.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
NOC clock by default is running @400MHz, to achieve
best DDR access performance, increase it to 800MHz.
With CPU @1.2GHz, we can see stream copy performance
increase 24% if NOC clock is increased from 400MHz
to 800MHz.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
add audio ipg clock, sai ipg clock and correct some wrong
place in clock tree.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Only enable the system critical clks by default, other clks only
need to be enabled when it is used by the driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Bai Ping