286 lines
7.3 KiB
C
286 lines
7.3 KiB
C
/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-mixel-lvds-combo.h>
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#include <linux/platform_device.h>
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/* Control and Status Registers(CSR) */
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#define PHY_CTRL 0x00
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#define CCM(n) (((n) & 0x7) << 5)
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#define CCM_MASK 0xe0
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#define CA(n) (((n) & 0x7) << 2)
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#define CA_MASK 0x1c
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#define RFB BIT(1)
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#define LVDS_EN BIT(0)
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#define SS 0x20
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#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
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#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
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#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
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#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
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#define ULPS 0x30
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#define ULPS_MASK 0x1f
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#define LANE(n) BIT(n)
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#define DPI 0x40
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#define COLOR_CODE_MASK 0x7
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#define BIT16_CFG1 0x0
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#define BIT16_CFG2 0x1
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#define BIT16_CFG3 0x2
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#define BIT18_CFG1 0x3
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#define BIT18_CFG2 0x4
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#define BIT24 0x5
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/* controller registers */
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#define PD_TX 0x300
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#define PD_PLL 0x31c
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struct mixel_lvds_phy {
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struct device *dev;
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void __iomem *csr_base;
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void __iomem *ctrl_base;
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struct mutex lock;
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struct phy *phy;
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struct clk *phy_clk;
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};
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static inline u32 phy_csr_read(struct phy *phy, unsigned int reg)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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return readl(lvds_phy->csr_base + reg);
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}
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static inline void phy_csr_write(struct phy *phy, u32 value, unsigned int reg)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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writel(value, lvds_phy->csr_base + reg);
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}
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static inline u32 phy_ctrl_read(struct phy *phy, unsigned int reg)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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return readl(lvds_phy->ctrl_base + reg);
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}
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static inline void phy_ctrl_write(struct phy *phy, u32 value, unsigned int reg)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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writel(value, lvds_phy->ctrl_base + reg);
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}
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void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy,
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unsigned long phy_clk_rate)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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/*
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* To workaround setting clock rate failure issue
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* when the system resumes back from PM sleep mode,
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* we need to get the clock rate before setting it's
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* rate, otherwise, setting the clock rate will fail.
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*/
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clk_get_rate(lvds_phy->phy_clk);
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clk_set_rate(lvds_phy->phy_clk, phy_clk_rate);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_phy_speed);
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void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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u32 val;
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clk_prepare_enable(lvds_phy->phy_clk);
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mutex_lock(&lvds_phy->lock);
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val = phy_csr_read(phy, SS);
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val &= ~(CH_HSYNC_M(0) | CH_HSYNC_M(1));
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if (active_high)
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val |= (CH_PHSYNC(0) | CH_PHSYNC(1));
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phy_csr_write(phy, val, SS);
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mutex_unlock(&lvds_phy->lock);
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clk_disable_unprepare(lvds_phy->phy_clk);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_hsync_pol);
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void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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u32 val;
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clk_prepare_enable(lvds_phy->phy_clk);
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mutex_lock(&lvds_phy->lock);
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val = phy_csr_read(phy, SS);
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val &= ~(CH_VSYNC_M(0) | CH_VSYNC_M(1));
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if (active_high)
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val |= (CH_PVSYNC(0) | CH_PVSYNC(1));
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phy_csr_write(phy, val, SS);
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mutex_unlock(&lvds_phy->lock);
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clk_disable_unprepare(lvds_phy->phy_clk);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_vsync_pol);
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static int mixel_lvds_combo_phy_init(struct phy *phy)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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u32 val;
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clk_prepare_enable(lvds_phy->phy_clk);
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mutex_lock(&lvds_phy->lock);
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val = phy_csr_read(phy, PHY_CTRL);
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val &= ~(CCM_MASK | CA_MASK);
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val |= (CCM(0x5) | CA(0x4) | RFB);
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phy_csr_write(phy, val, PHY_CTRL);
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val = phy_csr_read(phy, DPI);
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val &= ~COLOR_CODE_MASK;
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val |= BIT24;
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phy_csr_write(phy, val, DPI);
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mutex_unlock(&lvds_phy->lock);
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clk_disable_unprepare(lvds_phy->phy_clk);
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return 0;
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}
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static int mixel_lvds_combo_phy_power_on(struct phy *phy)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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u32 val;
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clk_prepare_enable(lvds_phy->phy_clk);
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mutex_lock(&lvds_phy->lock);
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phy_ctrl_write(phy, 0, PD_PLL);
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phy_ctrl_write(phy, 0, PD_TX);
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val = phy_csr_read(phy, ULPS);
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val &= ~ULPS_MASK;
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phy_csr_write(phy, val, ULPS);
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val = phy_csr_read(phy, PHY_CTRL);
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val |= LVDS_EN;
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phy_csr_write(phy, val, PHY_CTRL);
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mutex_unlock(&lvds_phy->lock);
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usleep_range(500, 1000);
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return 0;
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}
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static int mixel_lvds_combo_phy_power_off(struct phy *phy)
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{
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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u32 val;
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mutex_lock(&lvds_phy->lock);
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val = phy_csr_read(phy, PHY_CTRL);
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val &= ~LVDS_EN;
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phy_csr_write(phy, val, PHY_CTRL);
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val = phy_csr_read(phy, ULPS);
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val |= ULPS_MASK;
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phy_csr_write(phy, val, ULPS);
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phy_ctrl_write(phy, 1, PD_TX);
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phy_ctrl_write(phy, 1, PD_PLL);
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mutex_unlock(&lvds_phy->lock);
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clk_disable_unprepare(lvds_phy->phy_clk);
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return 0;
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}
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static const struct phy_ops mixel_lvds_combo_phy_ops = {
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.init = mixel_lvds_combo_phy_init,
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.power_on = mixel_lvds_combo_phy_power_on,
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.power_off = mixel_lvds_combo_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int mixel_lvds_combo_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct phy_provider *phy_provider;
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struct mixel_lvds_phy *lvds_phy;
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lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
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if (!lvds_phy)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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lvds_phy->csr_base = devm_ioremap(dev, res->start, SZ_256);
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if (!lvds_phy->csr_base)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res)
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return -ENODEV;
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lvds_phy->ctrl_base = devm_ioremap(dev, res->start, SZ_4K);
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if (!lvds_phy->ctrl_base)
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return -ENOMEM;
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lvds_phy->phy_clk = devm_clk_get(dev, "phy");
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if (IS_ERR(lvds_phy->phy_clk)) {
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dev_err(dev, "cannot get phy clock\n");
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return PTR_ERR(lvds_phy->phy_clk);
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}
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lvds_phy->dev = dev;
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mutex_init(&lvds_phy->lock);
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lvds_phy->phy = devm_phy_create(dev, NULL, &mixel_lvds_combo_phy_ops);
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if (IS_ERR(lvds_phy->phy)) {
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dev_err(dev, "failed to create phy\n");
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return PTR_ERR(lvds_phy->phy);
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}
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phy_set_drvdata(lvds_phy->phy, lvds_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id mixel_lvds_combo_phy_of_match[] = {
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{ .compatible = "mixel,lvds-combo-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, mixel_lvds_combo_phy_of_match);
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static struct platform_driver mixel_lvds_combo_phy_driver = {
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.probe = mixel_lvds_combo_phy_probe,
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.driver = {
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.name = "mixel-lvds-combo-phy",
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.of_match_table = mixel_lvds_combo_phy_of_match,
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}
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};
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module_platform_driver(mixel_lvds_combo_phy_driver);
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MODULE_AUTHOR("NXP Semiconductor");
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MODULE_DESCRIPTION("Mixel LVDS combo PHY driver");
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MODULE_LICENSE("GPL v2");
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