![Thomas Petazzoni](/assets/img/avatar_default.png)
Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER enabled, even for non-DT platforms (if we want both DT and non-DT platforms to be supported in a single kernel). However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT platforms in plat-orion/irq.c doesn't match the needs of Orion5x. Also, it doesn't make much sense for orion_irq_init() to register the multi-IRQ handler: orion_irq_init() is called once for each IRQ cause/mask tuple, while the multi-IRQ handler only needs to be registered once. To solve this problem, we move the multi-IRQ handle in per-platform code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant will be introduced in a followup commit. Of course, this code will ultimately be completely removed once all boards are converted to the Device Tree. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-23-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
179 lines
3.9 KiB
C
179 lines
3.9 KiB
C
/*
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* arch/arm/mach-dove/irq.c
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*
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* Dove IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <plat/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/pm.h>
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#include <mach/bridge-regs.h>
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#include <plat/orion-gpio.h>
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#include "common.h"
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static void pmu_irq_mask(struct irq_data *d)
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{
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int pin = irq_to_pmu(d->irq);
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u32 u;
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u = readl(PMU_INTERRUPT_MASK);
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u &= ~(1 << (pin & 31));
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writel(u, PMU_INTERRUPT_MASK);
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}
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static void pmu_irq_unmask(struct irq_data *d)
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{
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int pin = irq_to_pmu(d->irq);
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u32 u;
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u = readl(PMU_INTERRUPT_MASK);
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u |= 1 << (pin & 31);
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writel(u, PMU_INTERRUPT_MASK);
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}
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static void pmu_irq_ack(struct irq_data *d)
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{
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int pin = irq_to_pmu(d->irq);
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u32 u;
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/*
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* The PMU mask register is not RW0C: it is RW. This means that
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* the bits take whatever value is written to them; if you write
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* a '1', you will set the interrupt.
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*
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* Unfortunately this means there is NO race free way to clear
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* these interrupts.
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*
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* So, let's structure the code so that the window is as small as
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* possible.
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*/
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u = ~(1 << (pin & 31));
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u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
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writel_relaxed(u, PMU_INTERRUPT_CAUSE);
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}
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static struct irq_chip pmu_irq_chip = {
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.name = "pmu_irq",
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.irq_mask = pmu_irq_mask,
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.irq_unmask = pmu_irq_unmask,
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.irq_ack = pmu_irq_ack,
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};
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static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
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cause &= readl(PMU_INTERRUPT_MASK);
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if (cause == 0) {
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do_bad_IRQ(irq, desc);
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return;
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}
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for (irq = 0; irq < NR_PMU_IRQS; irq++) {
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if (!(cause & (1 << irq)))
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continue;
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irq = pmu_to_irq(irq);
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generic_handle_irq(irq);
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}
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}
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static int __initdata gpio0_irqs[4] = {
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IRQ_DOVE_GPIO_0_7,
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IRQ_DOVE_GPIO_8_15,
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IRQ_DOVE_GPIO_16_23,
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IRQ_DOVE_GPIO_24_31,
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};
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static int __initdata gpio1_irqs[4] = {
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IRQ_DOVE_HIGH_GPIO,
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0,
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0,
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0,
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};
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static int __initdata gpio2_irqs[4] = {
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0,
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0,
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0,
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0,
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};
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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/*
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* Compiling with both non-DT and DT support enabled, will
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* break asm irq handler used by non-DT boards. Therefore,
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* we provide a C-style irq handler even for non-DT boards,
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* if MULTI_IRQ_HANDLER is set.
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*/
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static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
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static asmlinkage void
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__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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#endif
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void __init dove_init_irq(void)
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{
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int i;
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orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(dove_legacy_handle_irq);
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#endif
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/*
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* Initialize gpiolib for GPIOs 0-71.
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*/
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orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
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IRQ_DOVE_GPIO_START, gpio0_irqs);
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orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
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IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
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orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
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IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
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/*
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* Mask and clear PMU interrupts
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*/
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writel(0, PMU_INTERRUPT_MASK);
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writel(0, PMU_INTERRUPT_CAUSE);
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for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
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irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
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irq_set_status_flags(i, IRQ_LEVEL);
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set_irq_flags(i, IRQF_VALID);
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}
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irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
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}
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