![Martin Fuzzey](/assets/img/avatar_default.png)
ARMv7 counters other than the CPU cycle counter only work if the Secure Debug Enable Register (SDER) SUNIDEN bit is set. Since access to the SDER is only possible in secure state, it will only be done if the device tree property "secure-reg-access" is set. Without this: Performance counter stats for 'sleep 1': 14606094 cycles # 0.000 GHz 0 instructions # 0.00 insns per cycle After applying: Performance counter stats for 'sleep 1': 5843809 cycles 2566484 instructions # 0.44 insns per cycle 1.020144000 seconds time elapsed Some platforms (eg i.MX53) may also need additional platform specific setup. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com> Signed-off-by: George G. Davis <george_davis@mentor.com> [will: add warning if property is found on arm64] Signed-off-by: Will Deacon <will.deacon@arm.com>
934 lines
22 KiB
C
934 lines
22 KiB
C
#undef DEBUG
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/*
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* ARM performance counter support.
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*
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
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* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
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*
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* This code is based on the sparc64 perf event code, which is in turn based
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* on the x86 code.
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*/
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#define pr_fmt(fmt) "hw perfevents: " fmt
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#include <linux/bitmap.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/of_device.h>
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#include <linux/perf/arm_pmu.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <asm/cputype.h>
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#include <asm/irq_regs.h>
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static int
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armpmu_map_cache_event(const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u64 config)
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{
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unsigned int cache_type, cache_op, cache_result, ret;
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cache_type = (config >> 0) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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cache_op = (config >> 8) & 0xff;
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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cache_result = (config >> 16) & 0xff;
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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return ret;
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}
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static int
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armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
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{
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int mapping;
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if (config >= PERF_COUNT_HW_MAX)
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return -EINVAL;
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mapping = (*event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
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}
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static int
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armpmu_map_raw_event(u32 raw_event_mask, u64 config)
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{
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return (int)(config & raw_event_mask);
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}
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int
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armpmu_map_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u32 raw_event_mask)
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{
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u64 config = event->attr.config;
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int type = event->attr.type;
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if (type == event->pmu->type)
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return armpmu_map_raw_event(raw_event_mask, config);
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switch (type) {
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case PERF_TYPE_HARDWARE:
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return armpmu_map_hw_event(event_map, config);
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case PERF_TYPE_HW_CACHE:
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return armpmu_map_cache_event(cache_map, config);
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case PERF_TYPE_RAW:
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return armpmu_map_raw_event(raw_event_mask, config);
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}
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return -ENOENT;
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}
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int armpmu_event_set_period(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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/*
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* Limit the maximum period to prevent the counter value
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* from overtaking the one we are about to program. In
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* effect we are reducing max_period to account for
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* interrupt latency (and we are being very conservative).
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*/
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if (left > (armpmu->max_period >> 1))
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left = armpmu->max_period >> 1;
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local64_set(&hwc->prev_count, (u64)-left);
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armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
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perf_event_update_userpage(event);
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return ret;
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}
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u64 armpmu_event_update(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = armpmu->read_counter(event);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return new_raw_count;
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}
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static void
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armpmu_read(struct perf_event *event)
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{
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armpmu_event_update(event);
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}
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static void
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armpmu_stop(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to update the counter, so ignore
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* PERF_EF_UPDATE, see comments in armpmu_start().
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*/
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if (!(hwc->state & PERF_HES_STOPPED)) {
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armpmu->disable(event);
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armpmu_event_update(event);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static void armpmu_start(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to reprogram the period, so ignore
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* PERF_EF_RELOAD, see the comment below.
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*/
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/*
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* Set the period again. Some counters can't be stopped, so when we
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* were stopped we simply disabled the IRQ source and the counter
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* may have been left counting. If we don't do this step then we may
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* get an interrupt too soon or *way* too late if the overflow has
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* happened since disabling.
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*/
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armpmu_event_set_period(event);
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armpmu->enable(event);
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}
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static void
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armpmu_del(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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armpmu_stop(event, PERF_EF_UPDATE);
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hw_events->events[idx] = NULL;
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clear_bit(idx, hw_events->used_mask);
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if (armpmu->clear_event_idx)
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armpmu->clear_event_idx(hw_events, event);
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perf_event_update_userpage(event);
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}
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static int
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armpmu_add(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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/* An event following a process won't be stopped earlier */
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if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
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return -ENOENT;
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perf_pmu_disable(event->pmu);
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/* If we don't have a space for the counter then finish early. */
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idx = armpmu->get_event_idx(hw_events, event);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then make
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* sure it is disabled.
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*/
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event->hw.idx = idx;
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armpmu->disable(event);
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hw_events->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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armpmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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perf_pmu_enable(event->pmu);
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return err;
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}
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static int
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validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
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struct perf_event *event)
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{
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struct arm_pmu *armpmu;
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if (is_software_event(event))
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return 1;
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/*
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* Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
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* core perf code won't check that the pmu->ctx == leader->ctx
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* until after pmu->event_init(event).
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*/
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if (event->pmu != pmu)
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return 0;
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if (event->state < PERF_EVENT_STATE_OFF)
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return 1;
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if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
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return 1;
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armpmu = to_arm_pmu(event->pmu);
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return armpmu->get_event_idx(hw_events, event) >= 0;
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}
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static int
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validate_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct pmu_hw_events fake_pmu;
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/*
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* Initialise the fake PMU. We only need to populate the
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* used_mask for the purposes of validation.
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*/
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memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
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if (!validate_event(event->pmu, &fake_pmu, leader))
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return -EINVAL;
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list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
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if (!validate_event(event->pmu, &fake_pmu, sibling))
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return -EINVAL;
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}
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if (!validate_event(event->pmu, &fake_pmu, event))
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return -EINVAL;
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return 0;
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}
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static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
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{
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struct arm_pmu *armpmu;
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struct platform_device *plat_device;
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struct arm_pmu_platdata *plat;
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int ret;
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u64 start_clock, finish_clock;
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/*
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* we request the IRQ with a (possibly percpu) struct arm_pmu**, but
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* the handlers expect a struct arm_pmu*. The percpu_irq framework will
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* do any necessary shifting, we just need to perform the first
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* dereference.
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*/
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armpmu = *(void **)dev;
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plat_device = armpmu->plat_device;
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plat = dev_get_platdata(&plat_device->dev);
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start_clock = sched_clock();
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if (plat && plat->handle_irq)
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ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
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else
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ret = armpmu->handle_irq(irq, armpmu);
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finish_clock = sched_clock();
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perf_sample_event_took(finish_clock - start_clock);
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return ret;
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}
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static void
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armpmu_release_hardware(struct arm_pmu *armpmu)
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{
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armpmu->free_irq(armpmu);
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}
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static int
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armpmu_reserve_hardware(struct arm_pmu *armpmu)
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{
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int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
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if (err) {
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armpmu_release_hardware(armpmu);
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return err;
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}
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return 0;
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}
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static void
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hw_perf_event_destroy(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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atomic_t *active_events = &armpmu->active_events;
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struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
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if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
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armpmu_release_hardware(armpmu);
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mutex_unlock(pmu_reserve_mutex);
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}
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}
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static int
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event_requires_mode_exclusion(struct perf_event_attr *attr)
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{
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return attr->exclude_idle || attr->exclude_user ||
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attr->exclude_kernel || attr->exclude_hv;
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}
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static int
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__hw_perf_event_init(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int mapping;
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mapping = armpmu->map_event(event);
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if (mapping < 0) {
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pr_debug("event %x:%llx not supported\n", event->attr.type,
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event->attr.config);
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return mapping;
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}
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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*/
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hwc->idx = -1;
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hwc->config_base = 0;
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hwc->config = 0;
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hwc->event_base = 0;
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/*
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* Check whether we need to exclude the counter from certain modes.
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*/
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if ((!armpmu->set_event_filter ||
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armpmu->set_event_filter(hwc, &event->attr)) &&
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event_requires_mode_exclusion(&event->attr)) {
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pr_debug("ARM performance counters do not support "
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"mode exclusion\n");
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return -EOPNOTSUPP;
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}
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/*
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* Store the event encoding into the config_base field.
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*/
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hwc->config_base |= (unsigned long)mapping;
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if (!is_sampling_event(event)) {
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/*
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* For non-sampling runs, limit the sample_period to half
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* of the counter width. That way, the new counter value
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* is far less likely to overtake the previous one unless
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* you have some serious IRQ latency issues.
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*/
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hwc->sample_period = armpmu->max_period >> 1;
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hwc->last_period = hwc->sample_period;
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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if (event->group_leader != event) {
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if (validate_group(event) != 0)
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return -EINVAL;
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}
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return 0;
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}
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static int armpmu_event_init(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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int err = 0;
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atomic_t *active_events = &armpmu->active_events;
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/*
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* Reject CPU-affine events for CPUs that are of a different class to
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* that which this PMU handles. Process-following events (where
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* event->cpu == -1) can be migrated between CPUs, and thus we have to
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* reject them later (in armpmu_add) if they're scheduled on a
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* different class of CPU.
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*/
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if (event->cpu != -1 &&
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!cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
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return -ENOENT;
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/* does not support taken branch sampling */
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if (has_branch_stack(event))
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return -EOPNOTSUPP;
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if (armpmu->map_event(event) == -ENOENT)
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return -ENOENT;
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event->destroy = hw_perf_event_destroy;
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if (!atomic_inc_not_zero(active_events)) {
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mutex_lock(&armpmu->reserve_mutex);
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if (atomic_read(active_events) == 0)
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err = armpmu_reserve_hardware(armpmu);
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if (!err)
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atomic_inc(active_events);
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mutex_unlock(&armpmu->reserve_mutex);
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}
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if (err)
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return err;
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err = __hw_perf_event_init(event);
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if (err)
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hw_perf_event_destroy(event);
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return err;
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}
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static void armpmu_enable(struct pmu *pmu)
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{
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struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
|
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
|
|
|
/* For task-bound events we may be called on other CPUs */
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
return;
|
|
|
|
if (enabled)
|
|
armpmu->start(armpmu);
|
|
}
|
|
|
|
static void armpmu_disable(struct pmu *pmu)
|
|
{
|
|
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
|
|
|
/* For task-bound events we may be called on other CPUs */
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
return;
|
|
|
|
armpmu->stop(armpmu);
|
|
}
|
|
|
|
/*
|
|
* In heterogeneous systems, events are specific to a particular
|
|
* microarchitecture, and aren't suitable for another. Thus, only match CPUs of
|
|
* the same microarchitecture.
|
|
*/
|
|
static int armpmu_filter_match(struct perf_event *event)
|
|
{
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
|
unsigned int cpu = smp_processor_id();
|
|
return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
|
|
}
|
|
|
|
static void armpmu_init(struct arm_pmu *armpmu)
|
|
{
|
|
atomic_set(&armpmu->active_events, 0);
|
|
mutex_init(&armpmu->reserve_mutex);
|
|
|
|
armpmu->pmu = (struct pmu) {
|
|
.pmu_enable = armpmu_enable,
|
|
.pmu_disable = armpmu_disable,
|
|
.event_init = armpmu_event_init,
|
|
.add = armpmu_add,
|
|
.del = armpmu_del,
|
|
.start = armpmu_start,
|
|
.stop = armpmu_stop,
|
|
.read = armpmu_read,
|
|
.filter_match = armpmu_filter_match,
|
|
};
|
|
}
|
|
|
|
/* Set at runtime when we know what CPU type we are. */
|
|
static struct arm_pmu *__oprofile_cpu_pmu;
|
|
|
|
/*
|
|
* Despite the names, these two functions are CPU-specific and are used
|
|
* by the OProfile/perf code.
|
|
*/
|
|
const char *perf_pmu_name(void)
|
|
{
|
|
if (!__oprofile_cpu_pmu)
|
|
return NULL;
|
|
|
|
return __oprofile_cpu_pmu->name;
|
|
}
|
|
EXPORT_SYMBOL_GPL(perf_pmu_name);
|
|
|
|
int perf_num_counters(void)
|
|
{
|
|
int max_events = 0;
|
|
|
|
if (__oprofile_cpu_pmu != NULL)
|
|
max_events = __oprofile_cpu_pmu->num_events;
|
|
|
|
return max_events;
|
|
}
|
|
EXPORT_SYMBOL_GPL(perf_num_counters);
|
|
|
|
static void cpu_pmu_enable_percpu_irq(void *data)
|
|
{
|
|
int irq = *(int *)data;
|
|
|
|
enable_percpu_irq(irq, IRQ_TYPE_NONE);
|
|
}
|
|
|
|
static void cpu_pmu_disable_percpu_irq(void *data)
|
|
{
|
|
int irq = *(int *)data;
|
|
|
|
disable_percpu_irq(irq);
|
|
}
|
|
|
|
static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
|
|
{
|
|
int i, irq, irqs;
|
|
struct platform_device *pmu_device = cpu_pmu->plat_device;
|
|
struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
|
|
|
|
irqs = min(pmu_device->num_resources, num_possible_cpus());
|
|
|
|
irq = platform_get_irq(pmu_device, 0);
|
|
if (irq >= 0 && irq_is_percpu(irq)) {
|
|
on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
|
|
free_percpu_irq(irq, &hw_events->percpu_pmu);
|
|
} else {
|
|
for (i = 0; i < irqs; ++i) {
|
|
int cpu = i;
|
|
|
|
if (cpu_pmu->irq_affinity)
|
|
cpu = cpu_pmu->irq_affinity[i];
|
|
|
|
if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
|
|
continue;
|
|
irq = platform_get_irq(pmu_device, i);
|
|
if (irq >= 0)
|
|
free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
|
|
}
|
|
}
|
|
}
|
|
|
|
static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
|
|
{
|
|
int i, err, irq, irqs;
|
|
struct platform_device *pmu_device = cpu_pmu->plat_device;
|
|
struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
|
|
|
|
if (!pmu_device)
|
|
return -ENODEV;
|
|
|
|
irqs = min(pmu_device->num_resources, num_possible_cpus());
|
|
if (irqs < 1) {
|
|
pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
|
|
return 0;
|
|
}
|
|
|
|
irq = platform_get_irq(pmu_device, 0);
|
|
if (irq >= 0 && irq_is_percpu(irq)) {
|
|
err = request_percpu_irq(irq, handler, "arm-pmu",
|
|
&hw_events->percpu_pmu);
|
|
if (err) {
|
|
pr_err("unable to request IRQ%d for ARM PMU counters\n",
|
|
irq);
|
|
return err;
|
|
}
|
|
on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
|
|
} else {
|
|
for (i = 0; i < irqs; ++i) {
|
|
int cpu = i;
|
|
|
|
err = 0;
|
|
irq = platform_get_irq(pmu_device, i);
|
|
if (irq < 0)
|
|
continue;
|
|
|
|
if (cpu_pmu->irq_affinity)
|
|
cpu = cpu_pmu->irq_affinity[i];
|
|
|
|
/*
|
|
* If we have a single PMU interrupt that we can't shift,
|
|
* assume that we're running on a uniprocessor machine and
|
|
* continue. Otherwise, continue without this interrupt.
|
|
*/
|
|
if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
|
|
pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
|
|
irq, cpu);
|
|
continue;
|
|
}
|
|
|
|
err = request_irq(irq, handler,
|
|
IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
|
|
per_cpu_ptr(&hw_events->percpu_pmu, cpu));
|
|
if (err) {
|
|
pr_err("unable to request IRQ%d for ARM PMU counters\n",
|
|
irq);
|
|
return err;
|
|
}
|
|
|
|
cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* PMU hardware loses all context when a CPU goes offline.
|
|
* When a CPU is hotplugged back in, since some hardware registers are
|
|
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
|
|
* junk values out of them.
|
|
*/
|
|
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
int cpu = (unsigned long)hcpu;
|
|
struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
|
|
|
|
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
|
|
return NOTIFY_DONE;
|
|
|
|
if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
|
|
return NOTIFY_DONE;
|
|
|
|
if (pmu->reset)
|
|
pmu->reset(pmu);
|
|
else
|
|
return NOTIFY_DONE;
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
int err;
|
|
int cpu;
|
|
struct pmu_hw_events __percpu *cpu_hw_events;
|
|
|
|
cpu_hw_events = alloc_percpu(struct pmu_hw_events);
|
|
if (!cpu_hw_events)
|
|
return -ENOMEM;
|
|
|
|
cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
|
|
err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
|
|
if (err)
|
|
goto out_hw_events;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
|
|
raw_spin_lock_init(&events->pmu_lock);
|
|
events->percpu_pmu = cpu_pmu;
|
|
}
|
|
|
|
cpu_pmu->hw_events = cpu_hw_events;
|
|
cpu_pmu->request_irq = cpu_pmu_request_irq;
|
|
cpu_pmu->free_irq = cpu_pmu_free_irq;
|
|
|
|
/* Ensure the PMU has sane values out of reset. */
|
|
if (cpu_pmu->reset)
|
|
on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
|
|
cpu_pmu, 1);
|
|
|
|
/* If no interrupts available, set the corresponding capability flag */
|
|
if (!platform_get_irq(cpu_pmu->plat_device, 0))
|
|
cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
|
|
|
|
return 0;
|
|
|
|
out_hw_events:
|
|
free_percpu(cpu_hw_events);
|
|
return err;
|
|
}
|
|
|
|
static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
|
|
{
|
|
unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
|
|
free_percpu(cpu_pmu->hw_events);
|
|
}
|
|
|
|
/*
|
|
* CPU PMU identification and probing.
|
|
*/
|
|
static int probe_current_pmu(struct arm_pmu *pmu,
|
|
const struct pmu_probe_info *info)
|
|
{
|
|
int cpu = get_cpu();
|
|
unsigned int cpuid = read_cpuid_id();
|
|
int ret = -ENODEV;
|
|
|
|
pr_info("probing PMU on CPU %d\n", cpu);
|
|
|
|
for (; info->init != NULL; info++) {
|
|
if ((cpuid & info->mask) != info->cpuid)
|
|
continue;
|
|
ret = info->init(pmu);
|
|
break;
|
|
}
|
|
|
|
put_cpu();
|
|
return ret;
|
|
}
|
|
|
|
static int of_pmu_irq_cfg(struct arm_pmu *pmu)
|
|
{
|
|
int *irqs, i = 0;
|
|
bool using_spi = false;
|
|
struct platform_device *pdev = pmu->plat_device;
|
|
|
|
irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
|
|
if (!irqs)
|
|
return -ENOMEM;
|
|
|
|
do {
|
|
struct device_node *dn;
|
|
int cpu, irq;
|
|
|
|
/* See if we have an affinity entry */
|
|
dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
|
|
if (!dn)
|
|
break;
|
|
|
|
/* Check the IRQ type and prohibit a mix of PPIs and SPIs */
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq >= 0) {
|
|
bool spi = !irq_is_percpu(irq);
|
|
|
|
if (i > 0 && spi != using_spi) {
|
|
pr_err("PPI/SPI IRQ type mismatch for %s!\n",
|
|
dn->name);
|
|
kfree(irqs);
|
|
return -EINVAL;
|
|
}
|
|
|
|
using_spi = spi;
|
|
}
|
|
|
|
/* Now look up the logical CPU number */
|
|
for_each_possible_cpu(cpu) {
|
|
struct device_node *cpu_dn;
|
|
|
|
cpu_dn = of_cpu_device_node_get(cpu);
|
|
of_node_put(cpu_dn);
|
|
|
|
if (dn == cpu_dn)
|
|
break;
|
|
}
|
|
|
|
if (cpu >= nr_cpu_ids) {
|
|
pr_warn("Failed to find logical CPU for %s\n",
|
|
dn->name);
|
|
of_node_put(dn);
|
|
cpumask_setall(&pmu->supported_cpus);
|
|
break;
|
|
}
|
|
of_node_put(dn);
|
|
|
|
/* For SPIs, we need to track the affinity per IRQ */
|
|
if (using_spi) {
|
|
if (i >= pdev->num_resources) {
|
|
of_node_put(dn);
|
|
break;
|
|
}
|
|
|
|
irqs[i] = cpu;
|
|
}
|
|
|
|
/* Keep track of the CPUs containing this PMU type */
|
|
cpumask_set_cpu(cpu, &pmu->supported_cpus);
|
|
of_node_put(dn);
|
|
i++;
|
|
} while (1);
|
|
|
|
/* If we didn't manage to parse anything, claim to support all CPUs */
|
|
if (cpumask_weight(&pmu->supported_cpus) == 0)
|
|
cpumask_setall(&pmu->supported_cpus);
|
|
|
|
/* If we matched up the IRQ affinities, use them to route the SPIs */
|
|
if (using_spi && i == pdev->num_resources)
|
|
pmu->irq_affinity = irqs;
|
|
else
|
|
kfree(irqs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int arm_pmu_device_probe(struct platform_device *pdev,
|
|
const struct of_device_id *of_table,
|
|
const struct pmu_probe_info *probe_table)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
const int (*init_fn)(struct arm_pmu *);
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct arm_pmu *pmu;
|
|
int ret = -ENODEV;
|
|
|
|
pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
|
|
if (!pmu) {
|
|
pr_info("failed to allocate PMU device!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
armpmu_init(pmu);
|
|
|
|
if (!__oprofile_cpu_pmu)
|
|
__oprofile_cpu_pmu = pmu;
|
|
|
|
pmu->plat_device = pdev;
|
|
|
|
if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
|
|
init_fn = of_id->data;
|
|
|
|
pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
|
|
"secure-reg-access");
|
|
|
|
/* arm64 systems boot only as non-secure */
|
|
if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
|
|
pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
|
|
pmu->secure_access = false;
|
|
}
|
|
|
|
ret = of_pmu_irq_cfg(pmu);
|
|
if (!ret)
|
|
ret = init_fn(pmu);
|
|
} else {
|
|
ret = probe_current_pmu(pmu, probe_table);
|
|
cpumask_setall(&pmu->supported_cpus);
|
|
}
|
|
|
|
if (ret) {
|
|
pr_info("failed to probe PMU!\n");
|
|
goto out_free;
|
|
}
|
|
|
|
ret = cpu_pmu_init(pmu);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
|
|
if (ret)
|
|
goto out_destroy;
|
|
|
|
pr_info("enabled with %s PMU driver, %d counters available\n",
|
|
pmu->name, pmu->num_events);
|
|
|
|
return 0;
|
|
|
|
out_destroy:
|
|
cpu_pmu_destroy(pmu);
|
|
out_free:
|
|
pr_info("failed to register PMU devices!\n");
|
|
kfree(pmu);
|
|
return ret;
|
|
}
|