Consolidate bool type

'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>

README

@@ -1938,15 +1938,15 @@ CBFS (Coreboot Filesystem) support
 
 		I2C_READ
 
-		Code that returns TRUE if the I2C data line is high,
+		Code that returns true if the I2C data line is high,
-		FALSE if it is low.
+		false if it is low.
 
 		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 
 		I2C_SDA(bit)
 
-		If <bit> is TRUE, sets the I2C data line high. If it
+		If <bit> is true, sets the I2C data line high. If it
-		is FALSE, it clears it (low).
+		is false, it clears it (low).
 
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
@@ -1954,8 +1954,8 @@ CBFS (Coreboot Filesystem) support
 
 		I2C_SCL(bit)
 
-		If <bit> is TRUE, sets the I2C clock line high. If it
+		If <bit> is true, sets the I2C clock line high. If it
-		is FALSE, it clears it (low).
+		is false, it clears it (low).
 
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \

arch/arm/cpu/arm926ejs/spear/spear600.c

@@ -28,9 +28,6 @@
 #include <asm/arch/spr_misc.h>
 #include <asm/arch/spr_defs.h>
 
-#define FALSE				0
-#define TRUE				(!FALSE)
-
 static void sel_1v8(void)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -133,8 +130,8 @@ void soc_init(void)
 /*
  * xxx_boot_selected:
  *
- * return TRUE if the particular booting option is selected
+ * return true if the particular booting option is selected
- * return FALSE otherwise
+ * return false otherwise
  */
 static u32 read_bootstrap(void)
 {
@@ -150,18 +147,18 @@ int snor_boot_selected(void)
 		/* Check whether SNOR boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
 			CONFIG_SPEAR_ONLYSNORBOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int nand_boot_selected(void)
@@ -172,20 +169,20 @@ int nand_boot_selected(void)
 		/* Check whether NAND boot is selected */
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND8BOOT)
-			return TRUE;
+			return true;
 
 		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 			CONFIG_SPEAR_NORNAND16BOOT)
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int pnor_boot_selected(void)
 {
 	/* Parallel NOR boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int usb_boot_selected(void)
@@ -195,39 +192,39 @@ int usb_boot_selected(void)
 	if (USB_BOOT_SUPPORTED) {
 		/* Check whether USB boot is selected */
 		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 int tftp_boot_selected(void)
 {
 	/* TFTP boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int uart_boot_selected(void)
 {
 	/* UART boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int spi_boot_selected(void)
 {
 	/* SPI boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int i2c_boot_selected(void)
 {
 	/* I2C boot is not selected in any SPEAr600 revision */
-	return FALSE;
+	return false;
 }
 
 int mmc_boot_selected(void)
 {
-	return FALSE;
+	return false;
 }
 
 void plat_late_init(void)

arch/arm/cpu/arm926ejs/spear/spl_boot.c

@@ -120,7 +120,7 @@ u32 spl_boot(void)
 	/*
 	 * All the supported booting devices are listed here. Each of
 	 * the booting type supported by the platform would define the
-	 * macro xxx_BOOT_SUPPORTED to TRUE.
+	 * macro xxx_BOOT_SUPPORTED to true.
 	 */
 
 	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {

arch/blackfin/include/asm/posix_types.h

@@ -61,9 +61,6 @@ typedef unsigned int __kernel_gid32_t;
 typedef unsigned short __kernel_old_uid_t;
 typedef unsigned short __kernel_old_gid_t;
 
-#define BOOL_WAS_DEFINED
-typedef enum { false = 0, true = 1 } bool;
-
 #ifdef __GNUC__
 typedef long long __kernel_loff_t;
 #endif

arch/m68k/lib/interrupts.c

@@ -96,7 +96,7 @@ int disable_interrupts (void)
 	sr = get_sr ();
 	set_sr (sr | 0x0700);
 
-	return ((sr & 0x0700) == 0);	/* return TRUE, if interrupts were enabled before */
+	return ((sr & 0x0700) == 0);	/* return true, if interrupts were enabled before */
 }
 
 void int_handler (struct pt_regs *fp)

arch/nds32/lib/interrupts.c

@@ -59,7 +59,7 @@ void enable_interrupts(void)
 
 /*
  * disable interrupts
- * Return TRUE if GIE is enabled before we disable it.
+ * Return true if GIE is enabled before we disable it.
  */
 int disable_interrupts(void)
 {

arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -513,7 +513,7 @@ void fsl_serdes_init(void)
 	size_t arglen;
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
+	int need_serdes_a001;	/* true == need work-around for SERDES A001 */
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	char buffer[HWCONFIG_BUFFER_SIZE];

arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c

@@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))
 #define NUMMEMTESTS		8
 #define NUMMEMWORDS		8
 #define MAXBXCR			4
-#define TRUE			1
-#define FALSE			0
 
 /*
  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
@@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 	unsigned char num_of_bytes;
 	unsigned char total_size;
 
-	dimm_found = FALSE;
+	dimm_found = false;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		num_of_bytes = 0;
 		total_size = 0;
@@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated,
 		total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 
 		if ((num_of_bytes != 0) && (total_size != 0)) {
-			dimm_populated[dimm_num] = TRUE;
+			dimm_populated[dimm_num] = true;
-			dimm_found = TRUE;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated\n", dimm_num);
 		} else {
-			dimm_populated[dimm_num] = FALSE;
+			dimm_populated[dimm_num] = false;
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
 
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 		spd_ddr_init_hang ();
 	}
@@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated,
 	unsigned char dimm_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 			switch (dimm_type) {
 			case 7:
@@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated,
 	unsigned long voltage_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 			if (voltage_type != 0x04) {
 				printf("ERROR: DIMM %lu with unsupported voltage level.\n",
@@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * FIXME: assume the DDR SDRAMs in both banks are the same
 	 */
-	ecc_enabled = TRUE;
+	ecc_enabled = true;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 			if (ecc != 0x02) {
-				ecc_enabled = FALSE;
+				ecc_enabled = false;
 			}
 
 			/*
@@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated,
 	/*
 	 * program Memory Data Error Checking
 	 */
-	if (ecc_enabled == TRUE) {
+	if (ecc_enabled == true) {
 		cfg0 |= SDRAM_CFG0_MCHK_GEN;
 	} else {
 		cfg0 |= SDRAM_CFG0_MCHK_NON;
@@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated,
 	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 
 	for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 			switch (refresh_rate_type) {
 			case 0x00:
@@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated,
 	t_rp_ns = 0;
 	t_rcd_ns = 0;
 	t_ras_ns = 0;
-	cas_2_0_available = TRUE;
+	cas_2_0_available = true;
-	cas_2_5_available = TRUE;
+	cas_2_5_available = true;
-	cas_3_0_available = TRUE;
+	cas_3_0_available = true;
 	tcyc_2_0_ns_x_10 = 0;
 	tcyc_2_5_ns_x_10 = 0;
 	tcyc_3_0_ns_x_10 = 0;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 			t_rp_ns	 = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 			t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
@@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_3_0_available = FALSE;
+				cas_3_0_available = false;
 			}
 
 			if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
@@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_5_available = FALSE;
+				cas_2_5_available = false;
 			}
 
 			if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
@@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated,
 				if (cas_index != 0) {
 					cas_index++;
 				}
-				cas_2_0_available = FALSE;
+				cas_2_0_available = false;
 			}
 
 			break;
@@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated,
 	/*
 	 * Program SD_CASL field
 	 */
-	if ((cas_2_0_available == TRUE) &&
+	if ((cas_2_0_available == true) &&
 	    (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
-	} else if ((cas_2_5_available == TRUE) &&
+	} else if ((cas_2_5_available == true) &&
 		 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
-	} else if ((cas_3_0_available == TRUE) &&
+	} else if ((cas_3_0_available == true) &&
 		 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 		tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 	} else {
@@ -950,9 +948,9 @@ static void program_tr1(void)
 	current_fail_length = 0;
 	current_start = 0;
 	rdclt_offset = 0;
-	window_found = FALSE;
+	window_found = false;
-	fail_found = FALSE;
+	fail_found = false;
-	pass_found = FALSE;
+	pass_found = false;
 	debug("Starting memory test ");
 
 	for (k = 0; k < NUMHALFCYCLES; k++) {
@@ -963,8 +961,8 @@ static void program_tr1(void)
 			mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 
 			if (short_mem_test()) {
-				if (fail_found == TRUE) {
+				if (fail_found == true) {
-					pass_found = TRUE;
+					pass_found = true;
 					if (current_pass_length == 0) {
 						current_start = rdclt_offset + rdclt;
 					}
@@ -983,10 +981,10 @@ static void program_tr1(void)
 				current_fail_length++;
 
 				if (current_fail_length >= (dly_val>>2)) {
-					if (fail_found == FALSE) {
+					if (fail_found == false) {
-						fail_found = TRUE;
+						fail_found = true;
-					} else if (pass_found == TRUE) {
+					} else if (pass_found == true) {
-						window_found = TRUE;
+						window_found = true;
 						break;
 					}
 				}
@@ -994,9 +992,8 @@ static void program_tr1(void)
 		}
 		debug(".");
 
-		if (window_found == TRUE) {
+		if (window_found == true)
 			break;
-		}
 
 		tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
 		rdclt_offset += dly_val;
@@ -1006,7 +1003,7 @@ static void program_tr1(void)
 	/*
 	 * make sure we find the window
 	 */
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		printf("ERROR: Cannot determine a common read delay.\n");
 		spd_ddr_init_hang ();
 	}
@@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 	bank_base_addr = CONFIG_SYS_SDRAM_BASE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
 			num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
 			num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);

arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

@@ -241,13 +241,6 @@ void board_add_ram_info(int use_default)
 /*-----------------------------------------------------------------------------+
  * Defines
  *-----------------------------------------------------------------------------*/
-#ifndef	TRUE
-#define TRUE		1
-#endif
-#ifndef FALSE
-#define FALSE		0
-#endif
-
 #define SDRAM_DDR1	1
 #define SDRAM_DDR2	2
 #define SDRAM_NONE	0
@@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 	unsigned char num_of_bytes;
 	unsigned char total_size;
 
-	dimm_found = FALSE;
+	dimm_found = false;
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		num_of_bytes = 0;
 		total_size = 0;
@@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated,
 		      iic0_dimm_addr[dimm_num], total_size);
 
 		if ((num_of_bytes != 0) && (total_size != 0)) {
-			dimm_populated[dimm_num] = TRUE;
+			dimm_populated[dimm_num] = true;
-			dimm_found = TRUE;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated\n", dimm_num);
 		} else {
-			dimm_populated[dimm_num] = FALSE;
+			dimm_populated[dimm_num] = false;
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
 
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 		spd_ddr_init_hang ();
 	}
@@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated,
 	unsigned long dimm_type;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-		if (dimm_populated[dimm_num] == TRUE) {
+		if (dimm_populated[dimm_num] == true) {
 			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 			switch (dimm_type) {
 			case 1:
@@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated,
 	unsigned long val;
 
 #ifdef CONFIG_DDR_ECC
-	ecc_enabled = TRUE;
+	ecc_enabled = true;
 #else
-	ecc_enabled = FALSE;
+	ecc_enabled = false;
 #endif
-	dimm_32bit = FALSE;
+	dimm_32bit = false;
-	dimm_64bit = FALSE;
+	dimm_64bit = false;
-	buf0 = FALSE;
+	buf0 = false;
-	buf1 = FALSE;
+	buf1 = false;
 
 	/*------------------------------------------------------------------
 	 * Set memory controller options reg 1, SDRAM_MCOPT1.
@@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated,
 			/* test ecc support */
 			ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 			if (ecc != 0x02) /* ecc not supported */
-				ecc_enabled = FALSE;
+				ecc_enabled = false;
 
 			/* test bank count */
 			bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
@@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated,
 				if (registered == 1) { /* DDR2 always buffered */
 					/* TODO: what about above  comments ? */
 					mcopt1 |= SDRAM_MCOPT1_RDEN;
-					buf0 = TRUE;
+					buf0 = true;
 				} else {
 					/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 					if ((attribute & 0x02) == 0x00) {
 						/* buffered not supported */
-						buf0 = FALSE;
+						buf0 = false;
 					} else {
 						mcopt1 |= SDRAM_MCOPT1_RDEN;
-						buf0 = TRUE;
+						buf0 = true;
 					}
 				}
 			}
@@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated,
 				if (registered == 1) {
 					/* DDR2 always buffered */
 					mcopt1 |= SDRAM_MCOPT1_RDEN;
-					buf1 = TRUE;
+					buf1 = true;
 				} else {
 					if ((attribute & 0x02) == 0x00) {
 						/* buffered not supported */
-						buf1 = FALSE;
+						buf1 = false;
 					} else {
 						mcopt1 |= SDRAM_MCOPT1_RDEN;
-						buf1 = TRUE;
+						buf1 = true;
 					}
 				}
 			}
@@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated,
 			switch (data_width) {
 			case 72:
 			case 64:
-				dimm_64bit = TRUE;
+				dimm_64bit = true;
 				break;
 			case 40:
 			case 32:
-				dimm_32bit = TRUE;
+				dimm_32bit = true;
 				break;
 			default:
 				printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
@@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated,
 		}
 	}
 
-	if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
+	if ((dimm_64bit == true) && (dimm_32bit == true)) {
 		printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
 		spd_ddr_init_hang ();
-	}
+	} else if ((dimm_64bit == true) && (dimm_32bit == false)) {
-	else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
 		mcopt1 |= SDRAM_MCOPT1_DMWD_64;
-	} else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
+	} else if ((dimm_64bit == false) && (dimm_32bit == true)) {
 		mcopt1 |= SDRAM_MCOPT1_DMWD_32;
 	} else {
 		printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
 		spd_ddr_init_hang ();
 	}
 
-	if (ecc_enabled == TRUE)
+	if (ecc_enabled == true)
 		mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
 	else
 		mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
@@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated,
 			total_rank += dimm_rank;
 			total_dimm++;
 			if ((dimm_num == 0) && (total_dimm == 1))
-				firstSlot = TRUE;
+				firstSlot = true;
 			else
-				firstSlot = FALSE;
+				firstSlot = false;
 		}
 	}
 	if (dimm_type == SDRAM_DDR2) {
 		codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
-		if ((total_dimm == 1) && (firstSlot == TRUE)) {
+		if ((total_dimm == 1) && (firstSlot == true)) {
 			if (total_rank == 1) {	/* PUUU */
 				codt |= CALC_ODT_R(0);
 				modt0 = CALC_ODT_W(0);
@@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated,
 				modt2 = 0x00000000;
 				modt3 = 0x00000000;
 			}
-		} else if ((total_dimm == 1) && (firstSlot != TRUE)) {
+		} else if ((total_dimm == 1) && (firstSlot != true)) {
 			if (total_rank == 1) {	/* UUPU */
 				codt |= CALC_ODT_R(2);
 				modt0 = 0x00000000;
@@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated,
 	 * the dimm modules installed.
 	 *-----------------------------------------------------------------*/
 	t_wr_ns = 0;
-	cas_2_0_available = TRUE;
+	cas_2_0_available = true;
-	cas_2_5_available = TRUE;
+	cas_2_5_available = true;
-	cas_3_0_available = TRUE;
+	cas_3_0_available = true;
-	cas_4_0_available = TRUE;
+	cas_4_0_available = true;
-	cas_5_0_available = TRUE;
+	cas_5_0_available = true;
 	max_2_0_tcyc_ns_x_100 = 10;
 	max_2_5_tcyc_ns_x_100 = 10;
 	max_3_0_tcyc_ns_x_100 = 10;
 	max_4_0_tcyc_ns_x_100 = 10;
 	max_5_0_tcyc_ns_x_100 = 10;
-	sdram_ddr1 = TRUE;
+	sdram_ddr1 = true;
 
 	/* loop through all the DIMM slots on the board */
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		/* If a dimm is installed in a particular slot ... */
 		if (dimm_populated[dimm_num] != SDRAM_NONE) {
 			if (dimm_populated[dimm_num] == SDRAM_DDR1)
-				sdram_ddr1 = TRUE;
+				sdram_ddr1 = true;
 			else
-				sdram_ddr1 = FALSE;
+				sdram_ddr1 = false;
 
 			cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 			debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
@@ -1543,7 +1535,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_4_0_available = FALSE;
+					cas_4_0_available = false;
 				}
 
 				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
@@ -1554,7 +1546,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_3_0_available = FALSE;
+					cas_3_0_available = false;
 				}
 
 				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
@@ -1565,7 +1557,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_2_5_available = FALSE;
+					cas_2_5_available = false;
 				}
 
 				if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
@@ -1576,7 +1568,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_2_0_available = FALSE;
+					cas_2_0_available = false;
 				}
 			} else {
 				/*
@@ -1592,7 +1584,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_5_0_available = FALSE;
+					cas_5_0_available = false;
 				}
 
 				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
@@ -1603,7 +1595,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_4_0_available = FALSE;
+					cas_4_0_available = false;
 				}
 
 				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
@@ -1614,7 +1606,7 @@ static void program_mode(unsigned long *dimm_populated,
 				} else {
 					if (cas_index != 0)
 						cas_index++;
-					cas_3_0_available = FALSE;
+					cas_3_0_available = false;
 				}
 			}
 		}
@@ -1636,14 +1628,17 @@ static void program_mode(unsigned long *dimm_populated,
 	debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
 	debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
 
-	if (sdram_ddr1 == TRUE) { /* DDR1 */
+	if (sdram_ddr1 == true) { /* DDR1 */
-		if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
+		if ((cas_2_0_available == true) &&
+			(sdram_freq <= cycle_2_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
 			*selected_cas = DDR_CAS_2;
-		} else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
+		} else if ((cas_2_5_available == true) &&
+			(sdram_freq <= cycle_2_5_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
 			*selected_cas = DDR_CAS_2_5;
-		} else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+		} else if ((cas_3_0_available == true) &&
+			(sdram_freq <= cycle_3_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
 			*selected_cas = DDR_CAS_3;
 		} else {
@@ -1656,13 +1651,16 @@ static void program_mode(unsigned long *dimm_populated,
 		debug("cas_3_0_available=%d\n", cas_3_0_available);
 		debug("cas_4_0_available=%d\n", cas_4_0_available);
 		debug("cas_5_0_available=%d\n", cas_5_0_available);
-		if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+		if ((cas_3_0_available == true) &&
+			(sdram_freq <= cycle_3_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
 			*selected_cas = DDR_CAS_3;
-		} else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
+		} else if ((cas_4_0_available == true) &&
+			(sdram_freq <= cycle_4_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
 			*selected_cas = DDR_CAS_4;
-		} else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
+		} else if ((cas_5_0_available == true) &&
+			(sdram_freq <= cycle_5_0_clk)) {
 			mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
 			*selected_cas = DDR_CAS_5;
 		} else {
@@ -1677,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated,
 		}
 	}
 
-	if (sdram_ddr1 == TRUE)
+	if (sdram_ddr1 == true)
 		mmode |= SDRAM_MMODE_WR_DDR1;
 	else {
 
@@ -1851,16 +1849,16 @@ static void program_tr(unsigned long *dimm_populated,
 	t_wpc_ns = 0;
 	t_wtr_ns = 0;
 	t_rpc_ns = 0;
-	sdram_ddr1 = TRUE;
+	sdram_ddr1 = true;
 
 	/* loop through all the DIMM slots on the board */
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		/* If a dimm is installed in a particular slot ... */
 		if (dimm_populated[dimm_num] != SDRAM_NONE) {
 			if (dimm_populated[dimm_num] == SDRAM_DDR2)
-				sdram_ddr1 = TRUE;
+				sdram_ddr1 = true;
 			else
-				sdram_ddr1 = FALSE;
+				sdram_ddr1 = false;
 
 			t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
 			t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
@@ -1925,7 +1923,7 @@ static void program_tr(unsigned long *dimm_populated,
 		break;
 	}
 
-	if (sdram_ddr1 == TRUE) { /* DDR1 */
+	if (sdram_ddr1 == true) { /* DDR1 */
 		if (sdram_freq < 200000000) {
 			sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
 			sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
@@ -2548,8 +2546,8 @@ calibration_loop:
 	current_pass_length = 0;
 	current_fail_length = 0;
 	current_start = 0;
-	fail_found = FALSE;
+	fail_found = false;
-	pass_found = FALSE;
+	pass_found = false;
 
 	/*
 	 * get the delay line calibration register value
@@ -2570,8 +2568,8 @@ calibration_loop:
 		 * See if the rffd value passed.
 		 *-----------------------------------------------------------------*/
 		if (short_mem_test()) {
-			if (fail_found == TRUE) {
+			if (fail_found == true) {
-				pass_found = TRUE;
+				pass_found = true;
 				if (current_pass_length == 0)
 					current_start = rffd;
 
@@ -2589,11 +2587,10 @@ calibration_loop:
 			current_fail_length++;
 
 			if (current_fail_length >= (dly_val >> 2)) {
-				if (fail_found == FALSE) {
+				if (fail_found == false)
-					fail_found = TRUE;
+					fail_found = true;
-				} else if (pass_found == TRUE) {
+				else if (pass_found == true)
 					break;
-				}
 			}
 		}
 	}		/* for rffd */
@@ -2618,9 +2615,9 @@ calibration_loop:
 	current_pass_length = 0;
 	current_fail_length = 0;
 	current_start = 0;
-	window_found = FALSE;
+	window_found = false;
-	fail_found = FALSE;
+	fail_found = false;
-	pass_found = FALSE;
+	pass_found = false;
 
 	for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
 		mfsdram(SDRAM_RQDC, rqdc_reg);
@@ -2635,8 +2632,8 @@ calibration_loop:
 		 * See if the rffd value passed.
 		 *-----------------------------------------------------------------*/
 		if (short_mem_test()) {
-			if (fail_found == TRUE) {
+			if (fail_found == true) {
-				pass_found = TRUE;
+				pass_found = true;
 				if (current_pass_length == 0)
 					current_start = rqfd;
 
@@ -2653,10 +2650,10 @@ calibration_loop:
 			current_pass_length = 0;
 			current_fail_length++;
 
-			if (fail_found == FALSE) {
+			if (fail_found == false) {
-				fail_found = TRUE;
+				fail_found = true;
-			} else if (pass_found == TRUE) {
+			} else if (pass_found == true) {
-				window_found = TRUE;
+				window_found = true;
 				break;
 			}
 		}
@@ -2667,7 +2664,7 @@ calibration_loop:
 	/*------------------------------------------------------------------
 	 * Make sure we found the valid read passing window.  Halt if not
 	 *-----------------------------------------------------------------*/
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
 			putc('\b');
 			putc(slash[loopi++ % 8]);
@@ -2769,13 +2766,13 @@ static void test(void)
 	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
 		SDRAM_MCOPT1_MCHK_NON);
 
-	window_found = FALSE;
+	window_found = false;
-	begin_found[0] = FALSE;
+	begin_found[0] = false;
-	end_found[0] = FALSE;
+	end_found[0] = false;
-	search_end[0] = FALSE;
+	search_end[0] = false;
-	begin_found[1] = FALSE;
+	begin_found[1] = false;
-	end_found[1] = FALSE;
+	end_found[1] = false;
-	search_end[1] = FALSE;
+	search_end[1] = false;
 
 	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
 		mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
@@ -2812,32 +2809,32 @@ static void test(void)
 			 * See if the rffd value passed.
 			 *-----------------------------------------------------------------*/
 			if (i < NUMMEMTESTS) {
-				if ((end_found[dimm_num] == FALSE) &&
+				if ((end_found[dimm_num] == false) &&
-				    (search_end[dimm_num] == TRUE)) {
+				    (search_end[dimm_num] == true)) {
-					end_found[dimm_num] = TRUE;
+					end_found[dimm_num] = true;
 				}
-				if ((end_found[0] == TRUE) &&
+				if ((end_found[0] == true) &&
-				    (end_found[1] == TRUE))
+				    (end_found[1] == true))
 					break;
 			} else {
-				if (begin_found[dimm_num] == FALSE) {
+				if (begin_found[dimm_num] == false) {
-					begin_found[dimm_num] = TRUE;
+					begin_found[dimm_num] = true;
-					search_end[dimm_num] = TRUE;
+					search_end[dimm_num] = true;
 				}
 			}
 		} else {
-			begin_found[dimm_num] = TRUE;
+			begin_found[dimm_num] = true;
-			end_found[dimm_num] = TRUE;
+			end_found[dimm_num] = true;
 		}
 	}
 
-	if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
+	if ((begin_found[0] == true) && (begin_found[1] == true))
-		window_found = TRUE;
+		window_found = true;
 
 	/*------------------------------------------------------------------
 	 * Make sure we found the valid read passing window.  Halt if not
 	 *-----------------------------------------------------------------*/
-	if (window_found == FALSE) {
+	if (window_found == false) {
 		printf("ERROR: Cannot determine a common read delay for the "
 		       "DIMM(s) installed.\n");
 		spd_ddr_init_hang ();

arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

@@ -53,13 +53,6 @@
 /*-----------------------------------------------------------------------------+
  * Defines
  *-----------------------------------------------------------------------------*/
-#ifndef	TRUE
-#define TRUE		1
-#endif
-#ifndef FALSE
-#define FALSE		0
-#endif
-
 #define MAXDIMMS	2
 #define MAXRANKS	2
 
@@ -279,7 +272,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 			 unsigned long num_dimm_banks)
 {
 	unsigned long dimm_num;
-	unsigned long dimm_found = FALSE;
+	unsigned long dimm_found = false;
 	unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
 	unsigned char num_of_bytes;
 	unsigned char total_size;
@@ -334,7 +327,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 				       "\n\n");
 				spd_ddr_init_hang();
 			}
-			dimm_found = TRUE;
+			dimm_found = true;
 			debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
 			      "\n", dimm_num, ranks_on_dimm);
 			if (ranks_on_dimm > max_ranks_per_dimm) {
@@ -355,7 +348,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
 			debug("DIMM slot %lu: Not populated\n", dimm_num);
 		}
 	}
-	if (dimm_found == FALSE) {
+	if (dimm_found == false) {
 		printf("ERROR: No memory installed.\n");
 		printf("Install at least one DDR2 DIMM.\n\n");
 		spd_ddr_init_hang();
@@ -882,7 +875,7 @@ static void program_ddr0_22(unsigned long dimm_ranks[],
 			/* Check for ECC */
 			if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
 				  0x02)) {
-				ecc_available = FALSE;
+				ecc_available = false;
 			}
 		}
 	}

board/Marvell/common/memory.c

@@ -383,7 +383,7 @@ unsigned int memoryGetDeviceWidth (DEVICE device)
 * OUTPUT:
 *       None.
 * RETURN:
-*       False for invalid size, true otherwise.
+*       false for invalid size, true otherwise.
 *
 * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
 *
@@ -509,7 +509,7 @@ bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
 *       None.
 *
 * RETURN:
-*       False for invalid size, true otherwise.
+*       false for invalid size, true otherwise.
 *
 * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
 *
@@ -624,7 +624,7 @@ bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
 *       None.
 *
 * RETURN:
-*       False for invalid size, true otherwise.
+*       false for invalid size, true otherwise.
 *
 *******************************************************************************/
 bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
@@ -885,7 +885,7 @@ void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
 *       None.
 *
 * RETURN:
-*       False for invalid size, true otherwise.
+*       false for invalid size, true otherwise.
 *
 *******************************************************************************/
 bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
@@ -1380,7 +1380,7 @@ void MemoryEnableWindow (MEMORY_WINDOW window)
 * OUTPUT:
 *       None.
 * RETURN:
-*       True for a closed window, false otherwise .
+*       true for a closed window, false otherwise .
 *******************************************************************************/
 MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
 {

board/Marvell/db64360/mpsc.c

@@ -966,7 +966,7 @@ static int galmpsc_set_snoop (int mpsc, int value)
 *       None.
 *
 * RETURN:
-*       True for success, false otherwise.
+*       true for success, false otherwise.
 *
 *******************************************************************************/
 

board/Marvell/db64360/mv_eth.h

@@ -46,13 +46,6 @@
 **************************************************************************
 **************************************************************************
 *************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
 #ifndef MAX_SKB_FRAGS
 #define MAX_SKB_FRAGS 0

board/Marvell/db64460/mpsc.c

@@ -966,7 +966,7 @@ static int galmpsc_set_snoop (int mpsc, int value)
 *       None.
 *
 * RETURN:
-*       True for success, false otherwise.
+*       true for success, false otherwise.
 *
 *******************************************************************************/
 

board/Marvell/db64460/mv_eth.h

@@ -47,13 +47,6 @@
 **************************************************************************
 **************************************************************************
 *************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
 #ifndef MAX_SKB_FRAGS
 #define MAX_SKB_FRAGS 0

board/Marvell/include/core.h

@@ -91,11 +91,6 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
 #define _1G		0x40000000
 #define _2G		0x80000000
 
-#ifndef	BOOL_WAS_DEFINED
-#define BOOL_WAS_DEFINED
-typedef enum _bool{false,true} bool;
-#endif
-
 /* Little to Big endian conversion macros */
 
 #ifdef LE /* Little Endian */

board/amcc/bamboo/bamboo.c

@@ -477,16 +477,16 @@ int is_powerpc440ep_pass1(void)
 	pvr = get_pvr();
 
 	if (pvr == PVR_POWERPC_440EP_PASS1)
-		return TRUE;
+		return true;
 	else if (pvr == PVR_POWERPC_440EP_PASS2)
-		return FALSE;
+		return false;
 	else {
 		printf("brdutil error 3\n");
 		for (;;)
 			;
 	}
 
-	return(FALSE);
+	return false;
 }
 
 /*----------------------------------------------------------------------------+
@@ -495,9 +495,9 @@ int is_powerpc440ep_pass1(void)
 int is_nand_selected(void)
 {
 #ifdef CONFIG_BAMBOO_NAND
-	return TRUE;
+	return true;
 #else
-	return FALSE;
+	return false;
 #endif
 }
 
@@ -507,7 +507,7 @@ int is_nand_selected(void)
 unsigned char config_on_ebc_cs4_is_small_flash(void)
 {
 	/* Not implemented yet => returns constant value */
-	return TRUE;
+	return true;
 }
 
 /*----------------------------------------------------------------------------+
@@ -561,7 +561,7 @@ void ext_bus_cntlr_init(void)
 	/*-------------------------------------------------------------------------+
 	  |  PPC440EP Pass1
 	  +-------------------------------------------------------------------------*/
-	if (is_powerpc440ep_pass1() == TRUE) {
+	if (is_powerpc440ep_pass1() == true) {
 		switch(bootstrap_settings) {
 		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
@@ -738,7 +738,7 @@ void ext_bus_cntlr_init(void)
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
-		if ((is_nand_selected()) == TRUE) {
+		if ((is_nand_selected()) == true) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
@@ -765,7 +765,7 @@ void ext_bus_cntlr_init(void)
 		/*------------------------------------------------------------------------- */
 		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
-		if ((is_nand_selected()) == TRUE) {
+		if ((is_nand_selected()) == true) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
@@ -812,7 +812,7 @@ void ext_bus_cntlr_init(void)
 		ebc0_cs0_bnap_value = 0;
 		ebc0_cs0_bncr_value = 0;
 
-		if ((is_nand_selected()) == TRUE) {
+		if ((is_nand_selected()) == true) {
 			/* NAND Flash */
 			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
@@ -830,7 +830,7 @@ void ext_bus_cntlr_init(void)
 			ebc0_cs3_bncr_value = 0;
 		}
 
-		if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+		if ((config_on_ebc_cs4_is_small_flash()) == true) {
 			/* Small Flash */
 			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;

board/amcc/bamboo/bamboo.h

@@ -250,9 +250,6 @@
 #define	 PVR_POWERPC_440EP_PASS1    0x42221850
 #define	 PVR_POWERPC_440EP_PASS2    0x422218D3
 
-#define TRUE 1
-#define FALSE 0
-
 #define GPIO0		0
 #define GPIO1		1
 

board/amcc/yucca/yucca.c

@@ -47,9 +47,6 @@ void fpga_init (void);
 #define DEBUGF(fmt,args...)
 #endif
 
-#define FALSE	0
-#define TRUE	1
-
 int board_early_init_f (void)
 {
 /*----------------------------------------------------------------------------+

board/bf533-ezkit/flash-defines.h

@@ -32,8 +32,6 @@
 
 #define V_ULONG(a)		(*(volatile unsigned long *)( a ))
 #define V_BYTE(a)		(*(volatile unsigned char *)( a ))
-#define TRUE			0x1
-#define FALSE			0x0
 #define BUFFER_SIZE		0x80000
 #define NO_COMMAND		0
 #define GET_CODES		1

board/bf533-ezkit/flash.c

@@ -309,7 +309,7 @@ int read_flash(long nOffset, int *pnValue)
 	nValue = *(volatile unsigned short *)addr;
 	SSYNC();
 	*pnValue = nValue;
-	return TRUE;
+	return true;
 }
 
 int poll_toggle_bit(long lOffset)
@@ -398,7 +398,7 @@ int erase_block_flash(int nBlock, unsigned long address)
 	long ulSectorOff = 0x0;
 
 	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
-		return FALSE;
+		return false;
 
 	ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
 

board/bf533-stamp/video.h

@@ -9,9 +9,6 @@
 #define YELLOW  (0xD292D210)	/* yellow pixel pattern  */
 #define WHITE   (0xFE80FE80)	/* white pixel pattern   */
 
-#define true	1
-#define false	0
-
 typedef struct {
 	unsigned int sav;
 	unsigned int eav;

board/esd/common/lcd.c

@@ -260,7 +260,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 		/*
 		 * Big epson detected
 		 */
-		reg_byte_swap = FALSE;
+		reg_byte_swap = false;
 		palette_index = 0x1e2;
 		palette_value = 0x1e4;
 		lcd_depth = 16;
@@ -269,7 +269,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 		/*
 		 * Big epson detected (with register swap bug)
 		 */
-		reg_byte_swap = TRUE;
+		reg_byte_swap = true;
 		palette_index = 0x1e3;
 		palette_value = 0x1e5;
 		lcd_depth = 16;
@@ -278,7 +278,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 		/*
 		 * Small epson detected (704)
 		 */
-		reg_byte_swap = FALSE;
+		reg_byte_swap = false;
 		palette_index = 0x15;
 		palette_value = 0x17;
 		lcd_depth = 8;
@@ -287,7 +287,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 		/*
 		 * Small epson detected (705)
 		 */
-		reg_byte_swap = FALSE;
+		reg_byte_swap = false;
 		palette_index = 0x15;
 		palette_value = 0x17;
 		lcd_depth = 8;
@@ -300,7 +300,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
 			/*
 			 * S1D13505 detected
 			 */
-			reg_byte_swap = TRUE;
+			reg_byte_swap = true;
 			palette_index = 0x25;
 			palette_value = 0x27;
 			lcd_depth = 16;

board/esd/common/lcd.h

@@ -35,11 +35,6 @@
 #define LOAD_LONG(data)   SWAP_LONG(data)
 #define LOAD_SHORT(data)  SWAP_SHORT(data)
 
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
 #define S1D_WRITE_PALETTE(p,i,r,g,b)					\
 	{								\
 		out_8(&((uchar*)(p))[palette_index], (uchar)(i));	\

board/esd/cpci750/mpsc.c

@@ -967,7 +967,7 @@ static int galmpsc_set_snoop (int mpsc, int value)
 *       None.
 *
 * RETURN:
-*       True for success, false otherwise.
+*       true for success, false otherwise.
 *
 *******************************************************************************/
 

board/esd/cpci750/mv_eth.h

@@ -47,13 +47,6 @@
 **************************************************************************
 **************************************************************************
 *************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
 #ifndef MAX_SKB_FRAGS
 #define MAX_SKB_FRAGS 0

board/esd/dasa_sim/cmd_dasa_sim.c

@@ -30,10 +30,6 @@
 #define OK 0
 #define ERROR (-1)
 
-#define TRUE 1
-#define FALSE 0
-
-
 extern u_long pci9054_iobase;
 
 
@@ -97,7 +93,7 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value)
 		}
 	}
 
-	return TRUE;
+	return true;
 }
 
 

board/esd/pmc440/fpga.c

@@ -113,7 +113,7 @@ void fpga_serialslave_init(void)
 {
 	debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
 	      __LINE__);
-	fpga_pgm_fn(FALSE, FALSE, 0);	/* make sure program pin is inactive */
+	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
 }
 
 
@@ -188,7 +188,7 @@ int fpga_done_fn(int cookie)
 int fpga_pre_config_fn(int cookie)
 {
 	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(TRUE);
+	fpga_reset(true);
 
 	/* release init# */
 	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
@@ -213,9 +213,9 @@ int fpga_post_config_fn(int cookie)
 	/* enable PLD0..7 pins */
 	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
 
-	fpga_reset(TRUE);
+	fpga_reset(true);
 	udelay (100);
-	fpga_reset(FALSE);
+	fpga_reset(false);
 	udelay (100);
 
 	FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
@@ -296,7 +296,7 @@ void ngcc_fpga_serialslave_init(void)
 	      __FUNCTION__, __LINE__);
 
 	/* make sure program pin is inactive */
-	ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
+	ngcc_fpga_pgm_fn(false, false, 0);
 }
 
 /*
@@ -382,10 +382,10 @@ int ngcc_fpga_pre_config_fn(int cookie)
 	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
 	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
 
-	ngcc_fpga_reset(TRUE);
+	ngcc_fpga_reset(true);
 	FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
 
-	ngcc_fpga_reset(TRUE);
+	ngcc_fpga_reset(true);
 	return 0;
 }
 
@@ -401,7 +401,7 @@ int ngcc_fpga_post_config_fn(int cookie)
 	debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
 
 	udelay (100);
-	ngcc_fpga_reset(FALSE);
+	ngcc_fpga_reset(false);
 
 	FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
 

board/evb64260/eth_addrtbl.c

@@ -6,9 +6,6 @@
 #include "eth.h"
 #include "eth_addrtbl.h"
 
-#define TRUE 1
-#define FALSE 0
-
 #define PRINTF printf
 
 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
@@ -160,8 +157,8 @@ u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
  * rd   - the RD field in the address table.
  * Outputs
  * address table entry is added.
- * TRUE if success.
+ * true if success.
- * FALSE if table full
+ * false if table full
  */
 int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
 {
@@ -206,7 +203,7 @@ int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
 
 	if (i == HOP_NUMBER) {
 		PRINTF ("addGT64260addressTableEntry: table section is full\n");
-		return (FALSE);
+		return false;
 	}
 
 	/*
@@ -215,7 +212,7 @@ int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
 	entry->hi = newHi;
 	entry->lo = newLo;
 	DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
-	return (TRUE);
+	return true;
 }
 
 #endif /* CONFIG_GT_USE_MAC_HASH_TABLE */

board/gen860t/fpga.c

@@ -182,7 +182,7 @@ void fpga_selectmap_init (void)
 {
 	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
 		__LINE__);
-	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
+	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
 }
 
 
@@ -314,7 +314,7 @@ int fpga_abort_fn (int cookie)
 int fpga_pre_config_fn (int cookie)
 {
 	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset (TRUE);
+	fpga_reset(true);
 	return 0;
 }
 
@@ -328,9 +328,9 @@ int fpga_post_config_fn (int cookie)
 	int rc;
 
 	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset (TRUE);
+	fpga_reset(true);
 	udelay (1000);
-	fpga_reset (FALSE);
+	fpga_reset(false);
 	udelay (1000);
 
 	/*

board/matrix_vision/mvblx/mvblx.c

@@ -162,7 +162,7 @@ int board_eth_init(bd_t *bis)
 
 int overwrite_console(void)
 {
-	/* return TRUE if console should be overwritten */
+	/* return true if console should be overwritten */
 	return 0;
 }
 

board/mousse/flash.c

@@ -450,7 +450,7 @@ STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len)
 }
 
 /*
- * flashWritable returns TRUE if a range contains all F's.
+ * flashWritable returns true if a range contains all F's.
  */
 
 STATUS flashWritable (flash_dev_t * dev, int pos, int len)

board/mpl/common/isa.c

@@ -41,13 +41,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#ifndef	TRUE
-#define TRUE            1
-#endif
-#ifndef FALSE
-#define FALSE           0
-#endif
-
 #if defined(CONFIG_PIP405)
 
 extern int drv_isa_kbd_init (void);
@@ -116,9 +109,9 @@ unsigned char open_cfg_super_IO(int address)
 	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
 	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
 	if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
-		return TRUE;
+		return true;
 	else
-		return FALSE;
+		return false;
 }
 
 void close_cfg_super_IO(int address)
@@ -179,7 +172,7 @@ void isa_sio_loadtable(void)
 
 void isa_sio_setup(void)
 {
-	if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE)
+	if (open_cfg_super_IO(SIO_CFG_PORT) == true)
 	{
 		isa_sio_loadtable();
 		close_cfg_super_IO(0x3F0);

board/mpl/mip405/mip405.c

@@ -77,8 +77,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef SDRAM_DEBUG
 #define ENABLE_ECC /* for ecc boards */
-#define FALSE           0
-#define TRUE            1
 
 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
 #ifndef __ldiv_t_defined
@@ -771,7 +769,8 @@ int last_stage_init (void)
 
 int overwrite_console (void)
 {
-	return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);	/* return TRUE if console should be overwritten */
+	/* return true if console should be overwritten */
+	return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
 }
 
 

board/mpl/pip405/pip405.c

@@ -36,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef SDRAM_DEBUG
 
-#define FALSE           0
-#define TRUE            1
-
 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
 #ifndef __ldiv_t_defined
 typedef struct {
@@ -700,7 +697,8 @@ int misc_init_r (void)
 
 int overwrite_console (void)
 {
-	return (in8 (CONFIG_PORT_ADDR) & 0x1);	/* return TRUE if console should be overwritten */
+	/* return true if console should be overwritten */
+	return in8(CONFIG_PORT_ADDR) & 0x1;
 }
 
 
@@ -945,7 +943,7 @@ void print_pip405_info (void)
 
 void user_led0 (unsigned char on)
 {
-	if (on == TRUE)
+	if (on == true)
 		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
 	else
 		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
@@ -953,7 +951,7 @@ void user_led0 (unsigned char on)
 
 void user_led1 (unsigned char on)
 {
-	if (on == TRUE)
+	if (on == true)
 		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
 	else
 		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));

board/prodrive/p3mx/mpsc.c

@@ -962,7 +962,7 @@ static int galmpsc_set_snoop (int mpsc, int value)
 *       None.
 *
 * RETURN:
-*       True for success, false otherwise.
+*       true for success, false otherwise.
 *
 *******************************************************************************/
 

board/prodrive/p3mx/mv_eth.h

@@ -47,13 +47,6 @@
 **************************************************************************
 **************************************************************************
 *************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
 #ifndef MAX_SKB_FRAGS
 #define MAX_SKB_FRAGS 0

board/sacsng/clkinit.c

@@ -94,11 +94,11 @@ uint Daq_BRG_Get_Div16(uint brg)
 
      if (*brg_ptr & CPM_BRG_DIV16) {
 	 /* DIV16 active */
-	 return (TRUE);
+	 return true;
      }
      else {
 	 /* DIV16 inactive */
-	 return (FALSE);
+	 return false;
      }
 }
 

board/sacsng/clkinit.h

@@ -22,11 +22,6 @@
  * MA 02111-1307 USA
  */
 
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
 #define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
 
 #define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */

board/spear/x600/fpga.c

@@ -113,7 +113,7 @@ static int fpga_done_fn(int cookie)
 static int fpga_pre_config_fn(int cookie)
 {
 	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-	fpga_reset(TRUE);
+	fpga_reset(true);
 
 	return 0;
 }
@@ -128,9 +128,9 @@ static int fpga_post_config_fn(int cookie)
 
 	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
 
-	fpga_reset(TRUE);
+	fpga_reset(true);
 	udelay(100);
-	fpga_reset(FALSE);
+	fpga_reset(false);
 	udelay(100);
 
 	return rc;
@@ -200,7 +200,7 @@ static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
 static void fpga_serialslave_init(void)
 {
 	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
-	fpga_pgm_fn(FALSE, FALSE, 0);	/* make sure program pin is inactive */
+	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
 }
 
 static int expi_setup(int freq)

board/teejet/mt_ventoux/mt_ventoux.c

@@ -179,9 +179,9 @@ int fpga_post_config_fn(int cookie)
 {
 	debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
 
-	fpga_reset(TRUE);
+	fpga_reset(true);
 	udelay(100);
-	fpga_reset(FALSE);
+	fpga_reset(false);
 
 	return 0;
 }

common/bedbug.c

@@ -72,7 +72,7 @@ int downstring __P ((char *));
  *			F_INSTR		- output raw instruction.
  *			F_LINENO	- show line # info if available.
  *
- * Returns TRUE if the area was successfully disassembled or FALSE if
+ * Returns true if the area was successfully disassembled or false if
  * a problem was encountered with accessing the memory.
  */
 
@@ -137,8 +137,8 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr,
 	for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) {
 #ifdef USE_SOURCE_CODE
 		if (ctx.flags & F_LINENO) {
-			if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename,
+			if ((line_info_from_addr ((Elf32_Word) ctx.virtual,
-									  funcname, &line_no) == TRUE) &&
+				filename, funcname, &line_no) == true) &&
 				((line_no != last_line_no) ||
 				 (strcmp (last_funcname, funcname) != 0))) {
 				print_source_line (filename, funcname, line_no, pfunc);
@@ -154,15 +154,15 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr,
 #ifdef USE_SOURCE_CODE
 		if (ctx.flags & F_SYMBOL) {
 			if ((symname =
-				 symbol_name_from_addr ((Elf32_Word) ctx.virtual,
+				 symbol_name_from_addr((Elf32_Word) ctx.virtual,
-										TRUE, 0)) != 0) {
+						true, 0)) != 0) {
 				cursym = symname;
 				symoffset = 0;
 			} else {
 				if ((cursym == 0) &&
 					((symname =
-					  symbol_name_from_addr ((Elf32_Word) ctx.virtual,
+					  symbol_name_from_addr((Elf32_Word) ctx.virtual,
-											 FALSE, &symoffset)) != 0)) {
+						false, &symoffset)) != 0)) {
 					cursym = symname;
 				} else {
 					symoffset += 4;
@@ -205,7 +205,8 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr,
 		}
 
 		if (((ctx.flags & F_SIMPLE) == 0) ||
-			(ctx.op->hfunc == 0) || ((*ctx.op->hfunc) (&ctx) == FALSE)) {
+			(ctx.op->hfunc == 0) ||
+			((*ctx.op->hfunc) (&ctx) == false)) {
 			sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name);
 			ctx.datalen += 8;
 			print_operands (&ctx);
@@ -214,7 +215,7 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr,
 		(*pfunc) (ctx.data);
 	}
 
-	return TRUE;
+	return true;
 }								/* disppc */
 
 
@@ -364,10 +365,10 @@ int print_operands (struct ppc_ctx *ctx)
  *	value		The address of an unsigned long to be filled in
  *			with the value of the operand if it is found.  This
  *			will only be filled in if the function returns
- *			TRUE.  This may be passed as 0 if the value is
+ *			true.  This may be passed as 0 if the value is
  *			not required.
  *
- * Returns TRUE if the operand was found or FALSE if it was not.
+ * Returns true if the operand was found or false if it was not.
  */
 
 int get_operand_value (struct opcode *op, unsigned long instr,
@@ -379,7 +380,7 @@ int get_operand_value (struct opcode *op, unsigned long instr,
   /*------------------------------------------------------------*/
 
 	if (field > n_operands) {
-		return FALSE;			/* bad operand ?! */
+		return false;			/* bad operand ?! */
 	}
 
 	/* Walk through the operands and list each in order */
@@ -393,10 +394,10 @@ int get_operand_value (struct opcode *op, unsigned long instr,
 		if (value) {
 			*value = (instr >> opr->shift) & ((1 << opr->bits) - 1);
 		}
-		return TRUE;
+		return true;
 	}
 
-	return FALSE;
+	return false;
 }								/* operand_value */
 
 
@@ -649,7 +650,7 @@ int tbr_value (char *name)
  * Arguments:
  *	ctx		A pointer to the disassembler context record.
  *
- * Returns TRUE if the simpler form was printed or FALSE if it was not.
+ * Returns true if the simpler form was printed or false if it was not.
  */
 
 int handle_bc (struct ppc_ctx *ctx)
@@ -669,33 +670,33 @@ int handle_bc (struct ppc_ctx *ctx)
 
   /*------------------------------------------------------------*/
 
-	if (get_operand_value (ctx->op, ctx->instr, O_BO, &bo) == FALSE)
+	if (get_operand_value(ctx->op, ctx->instr, O_BO, &bo) == false)
-		return FALSE;
+		return false;
 
-	if (get_operand_value (ctx->op, ctx->instr, O_BI, &bi) == FALSE)
+	if (get_operand_value(ctx->op, ctx->instr, O_BI, &bi) == false)
-		return FALSE;
+		return false;
 
 	if ((bo == 12) && (bi == 0)) {
 		ctx->op = &blt;
 		sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
 		ctx->datalen += 8;
 		print_operands (ctx);
-		return TRUE;
+		return true;
 	} else if ((bo == 4) && (bi == 10)) {
 		ctx->op = &bne;
 		sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
 		ctx->datalen += 8;
 		print_operands (ctx);
-		return TRUE;
+		return true;
 	} else if ((bo == 16) && (bi == 0)) {
 		ctx->op = &bdnz;
 		sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
 		ctx->datalen += 8;
 		print_operands (ctx);
-		return TRUE;
+		return true;
 	}
 
-	return FALSE;
+	return false;
 }								/* handle_blt */
 
 
@@ -719,7 +720,7 @@ int handle_bc (struct ppc_ctx *ctx)
  *	pfunc		The address of a function to call to print the output.
  *
  *
- * Returns TRUE if it was able to output the line info, or false if it was
+ * Returns true if it was able to output the line info, or false if it was
  * not.
  */
 
@@ -734,7 +735,7 @@ int print_source_line (char *filename, char *funcname,
 	sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no);
 	(*pfunc) (out_buf);
 
-	return TRUE;
+	return true;
 }								/* print_source_line */
 
 
@@ -1039,14 +1040,14 @@ int downstring (char *s)
  * Arguments:
  *	nextaddr	The address (to be filled in) of the next
  *			instruction to execute.  This will only be a valid
- *			address if TRUE is returned.
+ *			address if true is returned.
  *
  *	step_over	A flag indicating how to compute addresses for
  *			branch statements:
- *			 TRUE  = Step over the branch (next)
+ *			 true  = Step over the branch (next)
- *			 FALSE = step into the branch (step)
+ *			 false = step into the branch (step)
  *
- * Returns TRUE if it was able to compute the address.  Returns FALSE if
+ * Returns true if it was able to compute the address.  Returns false if
  * it has a problem reading the current instruction or one of the registers.
  */
 
@@ -1075,7 +1076,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 
 	if (nextaddr == 0 || regs == 0) {
 		printf ("find_next_address: bad args");
-		return FALSE;
+		return false;
 	}
 
 	pc = regs->nip & 0xfffffffc;
@@ -1083,7 +1084,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 
 	if ((op = find_opcode (instr)) == (struct opcode *) 0) {
 		printf ("find_next_address: can't parse opcode 0x%lx", instr);
-		return FALSE;
+		return false;
 	}
 
 	ctr = regs->ctr;
@@ -1100,7 +1101,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 			!get_operand_value (op, instr, O_BI, &bi) ||
 			!get_operand_value (op, instr, O_AA, &aa) ||
 			!get_operand_value (op, instr, O_LK, &lk))
-			return FALSE;
+			return false;
 
 		if ((addr & (1 << 13)) != 0)
 			addr = addr - (1 << 14);
@@ -1116,7 +1117,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 		if (!get_operand_value (op, instr, O_LI, &addr) ||
 			!get_operand_value (op, instr, O_AA, &aa) ||
 			!get_operand_value (op, instr, O_LK, &lk))
-			return FALSE;
+			return false;
 
 		if ((addr & (1 << 23)) != 0)
 			addr = addr - (1 << 24);
@@ -1130,7 +1131,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 		if (!get_operand_value (op, instr, O_BO, &bo) ||
 			!get_operand_value (op, instr, O_BI, &bi) ||
 			!get_operand_value (op, instr, O_LK, &lk))
-			return FALSE;
+			return false;
 
 		addr = ctr;
 		aa = 1;
@@ -1143,7 +1144,7 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 		if (!get_operand_value (op, instr, O_BO, &bo) ||
 			!get_operand_value (op, instr, O_BI, &bi) ||
 			!get_operand_value (op, instr, O_LK, &lk))
-			return FALSE;
+			return false;
 
 		addr = lr;
 		aa = 1;
@@ -1227,12 +1228,12 @@ int find_next_address (unsigned char *nextaddr, int step_over,
 		step = next = pc + 4;
 	}
 
-	if (step_over == TRUE)
+	if (step_over == true)
 		*(unsigned long *) nextaddr = next;
 	else
 		*(unsigned long *) nextaddr = step;
 
-	return TRUE;
+	return true;
 }								/* find_next_address */
 
 

common/cmd_bedbug.c

@@ -292,7 +292,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 		return 1;
 	}
 
-	if (!find_next_address ((unsigned char *) &addr, FALSE, bug_ctx.regs))
+	if (!find_next_address((unsigned char *) &addr, false, bug_ctx.regs))
 		return 1;
 
 	if (bug_ctx.set)
@@ -323,7 +323,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 		return 1;
 	}
 
-	if (!find_next_address ((unsigned char *) &addr, TRUE, bug_ctx.regs))
+	if (!find_next_address((unsigned char *) &addr, true, bug_ctx.regs))
 		return 1;
 
 	if (bug_ctx.set)

common/cmd_fdc.c

@@ -39,13 +39,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#ifndef	TRUE
-#define TRUE            1
-#endif
-#ifndef FALSE
-#define FALSE           0
-#endif
-
 /*#if defined(CONFIG_CMD_DATE) */
 /*#include <rtc.h> */
 /*#endif */
@@ -214,9 +207,9 @@ int wait_for_fdc_int(void)
 		timeout--;
 		udelay(10);
 		if(timeout==0) /* timeout occured */
-			return FALSE;
+			return false;
 	}
-	return TRUE;
+	return true;
 }
 
 /* reads a byte from the FIFO of the FDC and checks direction and RQM bit
@@ -244,7 +237,7 @@ int fdc_need_more_output(void)
 			c=(unsigned char)read_fdc_byte();
 			printf("Error: more output: %x\n",c);
 	}
-	return TRUE;
+	return true;
 }
 
 
@@ -260,10 +253,10 @@ int write_fdc_byte(unsigned char val)
 		udelay(10);
 		fdc_need_more_output();
 		if(timeout==0) /* timeout occured */
-			return FALSE;
+			return false;
 	}
 	write_fdc_reg(FDC_FIFO,val);
-	return TRUE;
+	return true;
 }
 
 /* sets up all FDC commands and issues it to the FDC. If
@@ -344,9 +337,9 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 	}
 	for(i=0;i<pCMD->cmdlen;i++) {
 		/* PRINTF("write cmd%d = 0x%02X\n",i,pCMD->cmd[i]); */
-		if(write_fdc_byte(pCMD->cmd[i])==FALSE) {
+		if (write_fdc_byte(pCMD->cmd[i]) == false) {
 			PRINTF("Error: timeout while issue cmd%d\n",i);
-			return FALSE;
+			return false;
 		}
 	}
 	timeout=FDC_TIME_OUT;
@@ -355,12 +348,12 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 			timeout--;
 			if(timeout==0) {
 				PRINTF(" timeout while reading result%d MSR=0x%02X\n",i,read_fdc_reg(FDC_MSR));
-				return FALSE;
+				return false;
 			}
 		}
 		pCMD->result[i]=(unsigned char)read_fdc_byte();
 	}
-	return TRUE;
+	return true;
 }
 
 /* selects the drive assigned in the cmd structur and
@@ -391,9 +384,10 @@ void stop_fdc_drive(FDC_COMMAND_STRUCT *pCMD)
 int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 {
 	pCMD->cmd[COMMAND]=FDC_CMD_RECALIBRATE;
-	if(fdc_issue_cmd(pCMD,pFG)==FALSE)
+	if (fdc_issue_cmd(pCMD, pFG) == false)
-		return FALSE;
+		return false;
-	while(wait_for_fdc_int()!=TRUE);
+	while (wait_for_fdc_int() != true);
+
 	pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
 	return(fdc_issue_cmd(pCMD,pFG));
 }
@@ -403,9 +397,10 @@ int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 int fdc_seek(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
 {
 	pCMD->cmd[COMMAND]=FDC_CMD_SEEK;
-	if(fdc_issue_cmd(pCMD,pFG)==FALSE)
+	if (fdc_issue_cmd(pCMD, pFG) == false)
-		return FALSE;
+		return false;
-	while(wait_for_fdc_int()!=TRUE);
+	while (wait_for_fdc_int() != true);
+
 	pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
 	return(fdc_issue_cmd(pCMD,pFG));
 }
@@ -421,7 +416,7 @@ int fdc_terminate(FDC_COMMAND_STRUCT *pCMD)
 	for(i=0;i<7;i++) {
 		pCMD->result[i]=(unsigned char)read_fdc_byte();
 	}
-	return TRUE;
+	return true;
 }
 
 /* reads data from FDC, seek commands are issued automatic */
@@ -440,18 +435,18 @@ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT
 	retriesrw=0;
 	retriescal=0;
 	offset=0;
-	if(fdc_seek(pCMD,pFG)==FALSE) {
+	if (fdc_seek(pCMD, pFG) == false) {
 		stop_fdc_drive(pCMD);
 		if (flags)
 			enable_interrupts();
-		return FALSE;
+		return false;
 	}
 	if((pCMD->result[STATUS_0]&0x20)!=0x20) {
 		printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
 		stop_fdc_drive(pCMD);
 		if (flags)
 			enable_interrupts();
-		return FALSE;
+		return false;
 	}
 	/* now determine the next seek point */
 	/*	lastblk=pCMD->blnr + blocks; */
@@ -466,11 +461,11 @@ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT
 retryrw:
 		len=sect_size * readblk;
 		pCMD->cmd[COMMAND]=FDC_CMD_READ;
-		if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+		if (fdc_issue_cmd(pCMD, pFG) == false) {
 			stop_fdc_drive(pCMD);
 			if (flags)
 				enable_interrupts();
-			return FALSE;
+			return false;
 		}
 		for (i=0;i<len;i++) {
 			timeout=FDC_TIME_OUT;
@@ -492,15 +487,15 @@ retryrw:
 							stop_fdc_drive(pCMD);
 							if (flags)
 								enable_interrupts();
-							return FALSE;
+							return false;
 						}
 						else {
 							PRINTF(" trying to recalibrate Try %d\n",retriescal);
-							if(fdc_recalibrate(pCMD,pFG)==FALSE) {
+							if (fdc_recalibrate(pCMD, pFG) == false) {
 								stop_fdc_drive(pCMD);
 								if (flags)
 									enable_interrupts();
-								return FALSE;
+								return false;
 							}
 							retriesrw=0;
 							goto retrycal;
@@ -512,7 +507,7 @@ retryrw:
 					} /* else >FDC_RW_RETRIES */
 				}/* if output */
 				timeout--;
-			}while(TRUE);
+			} while (true);
 		} /* for len */
 		/* the last sector of a track or all data has been read,
 		 * we need to get the results */
@@ -530,22 +525,22 @@ retryrw:
 			readblk=blocks;
 retrycal:
 		/* a seek is necessary */
-		if(fdc_seek(pCMD,pFG)==FALSE) {
+		if (fdc_seek(pCMD, pFG) == false) {
 			stop_fdc_drive(pCMD);
 			if (flags)
 				enable_interrupts();
-			return FALSE;
+			return false;
 		}
 		if((pCMD->result[STATUS_0]&0x20)!=0x20) {
 			PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
 			stop_fdc_drive(pCMD);
-			return FALSE;
+			return false;
 		}
-	}while(TRUE); /* start over */
+	} while (true); /* start over */
 	stop_fdc_drive(pCMD); /* switch off drive */
 	if (flags)
 		enable_interrupts();
-	return TRUE;
+	return true;
 }
 
 /* Scan all drives and check if drive is present and disk is inserted */
@@ -559,20 +554,20 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 		pCMD->drive=drives;
 		select_fdc_drive(pCMD);
 		pCMD->blnr=0; /* set to the 1st block */
-		if(fdc_recalibrate(pCMD,pFG)==FALSE)
+		if (fdc_recalibrate(pCMD, pFG) == false)
 			continue;
 		if((pCMD->result[STATUS_0]&0x10)==0x10)
 			continue;
 		/* ok drive connected check for disk */
 		state|=(1<<drives);
 		pCMD->blnr=pFG->size; /* set to the last block */
-		if(fdc_seek(pCMD,pFG)==FALSE)
+		if (fdc_seek(pCMD, pFG) == false)
 			continue;
 		pCMD->blnr=0; /* set to the 1st block */
-		if(fdc_recalibrate(pCMD,pFG)==FALSE)
+		if (fdc_recalibrate(pCMD, pFG) == false)
 			continue;
 		pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
-		if(fdc_issue_cmd(pCMD,pFG)==FALSE)
+		if (fdc_issue_cmd(pCMD, pFG) == false)
 			continue;
 		state|=(0x10<<drives);
 	}
@@ -584,7 +579,7 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 			((state&(0x10<<i))==(0x10<<i)) ? pFG->name : "");
 	}
 	pCMD->flags=state;
-	return TRUE;
+	return true;
 }
 
 
@@ -611,9 +606,9 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 	write_fdc_reg(FDC_CCR,pFG->rate);
 	/* then initialize the DSR */
 	write_fdc_reg(FDC_DSR,pFG->rate);
-	if(wait_for_fdc_int()==FALSE) {
+	if (wait_for_fdc_int() == false) {
 			PRINTF("Time Out after writing CCR\n");
-			return FALSE;
+			return false;
 	}
 	/* now issue sense Interrupt and status command
 	 * assuming only one drive present (drive 0) */
@@ -621,7 +616,7 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 	for(i=0;i<4;i++) {
 		/* issue sense interrupt for all 4 possible drives */
 		pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
-		if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+		if (fdc_issue_cmd(pCMD, pFG) == false) {
 			PRINTF("Sense Interrupt for drive %d failed\n",i);
 		}
 	}
@@ -629,24 +624,24 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 	pCMD->drive=drive;
 	select_fdc_drive(pCMD);
 	pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
-	if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+	if (fdc_issue_cmd(pCMD, pFG) == false) {
 		PRINTF(" configure timeout\n");
 		stop_fdc_drive(pCMD);
-		return FALSE;
+		return false;
 	}
 	/* issue specify command */
 	pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY;
-	if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+	if (fdc_issue_cmd(pCMD, pFG) == false) {
 		PRINTF(" specify timeout\n");
 		stop_fdc_drive(pCMD);
-		return FALSE;
+		return false;
 
 	}
 	/* then, we clear the reset in the DOR */
 	/* fdc_check_drive(pCMD,pFG);	*/
 	/*	write_fdc_reg(FDC_DOR,0x04); */
 
-	return TRUE;
+	return true;
 }
 
 #if defined(CONFIG_CMD_FDOS)
@@ -664,30 +659,30 @@ int fdc_fdos_init (int drive)
 	FDC_COMMAND_STRUCT *pCMD = &cmd;
 
 	/* setup FDC and scan for drives  */
-	if(fdc_setup(drive,pCMD,pFG)==FALSE) {
+	if (fdc_setup(drive, pCMD, pFG) == false) {
 		printf("\n** Error in setup FDC **\n");
-		return FALSE;
+		return false;
 	}
-	if(fdc_check_drive(pCMD,pFG)==FALSE) {
+	if (fdc_check_drive(pCMD, pFG) == false) {
 		printf("\n** Error in check_drives **\n");
-		return FALSE;
+		return false;
 	}
 	if((pCMD->flags&(1<<drive))==0) {
 		/* drive not available */
 		printf("\n** Drive %d not available **\n",drive);
-		return FALSE;
+		return false;
 	}
 	if((pCMD->flags&(0x10<<drive))==0) {
 		/* no disk inserted */
 		printf("\n** No disk inserted in drive %d **\n",drive);
-		return FALSE;
+		return false;
 	}
 	/* ok, we have a valid source */
 	pCMD->drive=drive;
 
 	/* read first block */
 	pCMD->blnr=0;
-	return TRUE;
+	return true;
 }
 /**************************************************************************
 * int fdc_fdos_seek
@@ -747,11 +742,11 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return CMD_RET_USAGE;
 	}
 	/* setup FDC and scan for drives  */
-	if(fdc_setup(boot_drive,pCMD,pFG)==FALSE) {
+	if (fdc_setup(boot_drive, pCMD, pFG) == false) {
 		printf("\n** Error in setup FDC **\n");
 		return 1;
 	}
-	if(fdc_check_drive(pCMD,pFG)==FALSE) {
+	if (fdc_check_drive(pCMD, pFG) == false) {
 		printf("\n** Error in check_drives **\n");
 		return 1;
 	}
@@ -769,7 +764,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	pCMD->drive=boot_drive;
 	/* read first block */
 	pCMD->blnr=0;
-	if(fdc_read_data((unsigned char *)addr,1,pCMD,pFG)==FALSE) {
+	if (fdc_read_data((unsigned char *)addr, 1, pCMD, pFG) == false) {
 		printf("\nRead error:");
 		for(i=0;i<7;i++)
 			printf("result%d: 0x%02X\n",i,pCMD->result[i]);
@@ -801,7 +796,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		nrofblk++;
 	printf("Loading %ld Bytes (%d blocks) at 0x%08lx..\n",imsize,nrofblk,addr);
 	pCMD->blnr=0;
-	if(fdc_read_data((unsigned char *)addr,nrofblk,pCMD,pFG)==FALSE) {
+	if (fdc_read_data((unsigned char *)addr, nrofblk, pCMD, pFG) == false) {
 		/* read image block */
 		printf("\nRead error:");
 		for(i=0;i<7;i++)

common/cmd_scsi.c

@@ -110,7 +110,7 @@ void scsi_scan(int mode)
 		scsi_dev_desc[i].vendor[0]=0;
 		scsi_dev_desc[i].product[0]=0;
 		scsi_dev_desc[i].revision[0]=0;
-		scsi_dev_desc[i].removable=FALSE;
+		scsi_dev_desc[i].removable = false;
 		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
 		scsi_dev_desc[i].dev=i;
 		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
@@ -125,7 +125,7 @@ void scsi_scan(int mode)
 			pccb->pdata=(unsigned char *)&tempbuff;
 			pccb->datalen=512;
 			scsi_setup_inquiry(pccb);
-			if(scsi_exec(pccb)!=TRUE) {
+			if (scsi_exec(pccb) != true) {
 				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
 					debug ("Selection timeout ID %d\n",pccb->target);
 					continue; /* selection timeout => assuming no device present */
@@ -139,7 +139,7 @@ void scsi_scan(int mode)
 				continue; /* skip unknown devices */
 			}
 			if((modi&0x80)==0x80) /* drive is removable */
-				scsi_dev_desc[scsi_max_devs].removable=TRUE;
+				scsi_dev_desc[scsi_max_devs].removable=true;
 			/* get info for this device */
 			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
 				       &tempbuff[8], 8);
@@ -152,8 +152,8 @@ void scsi_scan(int mode)
 
 			pccb->datalen=0;
 			scsi_setup_test_unit_ready(pccb);
-			if(scsi_exec(pccb)!=TRUE) {
+			if (scsi_exec(pccb) != true) {
-				if(scsi_dev_desc[scsi_max_devs].removable==TRUE) {
+				if (scsi_dev_desc[scsi_max_devs].removable == true) {
 					scsi_dev_desc[scsi_max_devs].type=perq;
 					goto removable;
 				}
@@ -404,7 +404,7 @@ static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
 		debug("scsi_read_ext: startblk " LBAF
 		      ", blccnt %x buffer %lx\n",
 		      start, smallblks, buf_addr);
-		if(scsi_exec(pccb)!=TRUE) {
+		if (scsi_exec(pccb) != true) {
 			scsi_print_error(pccb);
 			blkcnt-=blks;
 			break;
@@ -458,7 +458,7 @@ static ulong scsi_write(int device, ulong blknr,
 		}
 		debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n",
 		      __func__, start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != TRUE) {
+		if (scsi_exec(pccb) != true) {
 			scsi_print_error(pccb);
 			blkcnt -= blks;
 			break;
@@ -521,7 +521,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
 	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 
 	pccb->datalen = 8;
-	if (scsi_exec(pccb) != TRUE)
+	if (scsi_exec(pccb) != true)
 		return 1;
 
 	*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
@@ -547,7 +547,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
 	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 
 	pccb->datalen = 16;
-	if (scsi_exec(pccb) != TRUE)
+	if (scsi_exec(pccb) != true)
 		return 1;
 
 	*capacity = ((uint64_t)pccb->pdata[0] << 56) |

common/dlmalloc.c

@@ -201,7 +201,7 @@
   MORECORE_FAILURE          (default: -1)
      The value returned upon failure of MORECORE.
   MORECORE_CLEARS           (default 1)
-     True (1) if the routine mapped to MORECORE zeroes out memory (which
+     true (1) if the routine mapped to MORECORE zeroes out memory (which
      holds for sbrk).
   DEFAULT_TRIM_THRESHOLD
   DEFAULT_TOP_PAD

common/dlmalloc.src

@@ -198,7 +198,7 @@
   MORECORE_FAILURE          (default: -1)
      The value returned upon failure of MORECORE.
   MORECORE_CLEARS           (default 1)
-     True (1) if the routine mapped to MORECORE zeroes out memory (which
+     true (1) if the routine mapped to MORECORE zeroes out memory (which
      holds for sbrk).
   DEFAULT_TRIM_THRESHOLD
   DEFAULT_TOP_PAD

drivers/bios_emulator/atibios.c

@@ -52,10 +52,6 @@
 /* Length of the BIOS image */
 #define MAX_BIOSLEN	    (128 * 1024L)
 
-/* Define some useful types and macros */
-#define true		    1
-#define false		    0
-
 /* Place to save PCI BAR's that we change and later restore */
 static u32 saveROMBaseAddress;
 static u32 saveBaseAddress10;
@@ -242,7 +238,7 @@ pcidev	- PCI device info for the video card on the bus to boot
 VGAInfo - BIOS emulator VGA info structure
 
 RETURNS:
-True if successfully initialised, false if not.
+true if successfully initialised, false if not.
 
 REMARKS:
 Loads and POST's the display controllers BIOS, directly from the BIOS
@@ -295,7 +291,7 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
 PARAMETERS:
 pcidev	    - PCI device info for the video card on the bus to boot
 pVGAInfo    - Place to return VGA info structure is requested
-cleanUp	    - True to clean up on exit, false to leave emulator active
+cleanUp	    - true to clean up on exit, false to leave emulator active
 
 REMARKS:
 Boots the PCI/AGP video card on the bus using the Video ROM BIOS image

drivers/bios_emulator/include/biosemu.h

@@ -127,9 +127,9 @@ biosmem_limit   - Limit of the BIOS image
 busmem_base     - Base of the VGA bus memory
 timer           - Timer used to emulate PC timer ports
 timer0          - Latched value for timer 0
-timer0Latched   - True if timer 0 value was just latched
+timer0Latched   - true if timer 0 value was just latched
 timer2          - Current value for timer 2
-emulateVGA      - True to emulate VGA I/O and memory accesses
+emulateVGA      - true to emulate VGA I/O and memory accesses
 ****************************************************************************/
 
 typedef struct {

drivers/bios_emulator/x86emu/debug.c

@@ -309,7 +309,7 @@ void x86emu_single_step(void)
 		case 'P':
 			noDecode = (noDecode) ? 0 : 1;
 			printk("Toggled decoding to %s\n",
-			       (noDecode) ? "FALSE" : "TRUE");
+			       (noDecode) ? "false" : "true");
 			break;
 		case 't':
 		case 0:

drivers/block/ahci.c

@@ -865,14 +865,14 @@ int scsi_exec(ccb *pccb)
 		break;
 	default:
 		printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
-		return FALSE;
+		return false;
 	}
 
 	if (ret) {
 		debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
-		return FALSE;
+		return false;
 	}
-	return TRUE;
+	return true;
 
 }
 

drivers/block/sata_dwc.c

@@ -360,7 +360,7 @@ int init_sata(int dev)
 	if (status == 0x7f) {
 		printf("Hard Disk not found.\n");
 		dev_state = SATA_NODEVICE;
-		rc = FALSE;
+		rc = false;
 		return rc;
 	}
 
@@ -381,7 +381,7 @@ int init_sata(int dev)
 			printf("** TimeOUT **\n");
 
 			dev_state = SATA_NODEVICE;
-			rc = FALSE;
+			rc = false;
 			return rc;
 		}
 		if ((i >= 100) && ((i % 100) == 0))
@@ -458,7 +458,7 @@ static int sata_dwc_softreset(struct ata_port *ap)
 	} else {
 		printf("No device found\n");
 		dev_state = SATA_NODEVICE;
-		return FALSE;
+		return false;
 	}
 
 	tmp = ATA_DEVICE_OBS;
@@ -737,7 +737,7 @@ static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
 	status = ata_busy_wait(ap, ATA_BUSY, 30000);
 	if (status & ATA_BUSY) {
 		printf("BSY = 0 check. timeout.\n");
-		rc = FALSE;
+		rc = false;
 		return rc;
 	}
 
@@ -987,7 +987,7 @@ unsigned ata_exec_internal(struct ata_device *dev,
 	status = ata_busy_wait(ap, ATA_BUSY, 300000);
 	if (status & ATA_BUSY) {
 		printf("BSY = 0 check. timeout.\n");
-		rc = FALSE;
+		rc = false;
 		return rc;
 	}
 
@@ -997,7 +997,7 @@ unsigned ata_exec_internal(struct ata_device *dev,
 	tag = ATA_TAG_INTERNAL;
 
 	if (test_and_set_bit(tag, &ap->qc_allocated)) {
-		rc = FALSE;
+		rc = false;
 		return rc;
 	}
 
@@ -1656,14 +1656,14 @@ static int check_sata_dev_state(void)
 
 		ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
 
-		if (ret == TRUE)
+		if (ret == true)
 			break;
 
 		i++;
 		if (i > (ATA_RESET_TIME * 100)) {
 			printf("** TimeOUT **\n");
 			dev_state = SATA_NODEVICE;
-			return FALSE;
+			return false;
 		}
 
 		if ((i >= 100) && ((i % 100) == 0))
@@ -1672,7 +1672,7 @@ static int check_sata_dev_state(void)
 
 	dev_state = SATA_READY;
 
-	return TRUE;
+	return true;
 }
 
 static unsigned int ata_dev_set_feature(struct ata_device *dev,
@@ -1772,7 +1772,7 @@ ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
 			blks = 0;
 		}
 
-		if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) {
+		if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) {
 			printf("sata_dwc : Hard disk read error.\n");
 			blkcnt -= blks;
 			break;
@@ -1795,7 +1795,7 @@ static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
 	int may_fallback = 1;
 
 	if (dev_state == SATA_ERROR)
-		return FALSE;
+		return false;
 
 	ata_dev_select(ap, dev->devno, 1, 1);
 
@@ -1893,11 +1893,11 @@ retry:
 		goto err_out;
 	}
 
-	return TRUE;
+	return true;
 
 err_out:
 	printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
-	return FALSE;
+	return false;
 }
 
 #if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
@@ -1946,7 +1946,7 @@ ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
 			blks = 0;
 		}
 
-		if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) {
+		if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) {
 			printf("sata_dwc : Hard disk read error.\n");
 			blkcnt -= blks;
 			break;
@@ -1969,7 +1969,7 @@ static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
 	int may_fallback = 1;
 
 	if (dev_state == SATA_ERROR)
-		return FALSE;
+		return false;
 
 	ata_dev_select(ap, dev->devno, 1, 1);
 
@@ -2068,9 +2068,9 @@ retry:
 		goto err_out;
 	}
 
-	return TRUE;
+	return true;
 
 err_out:
 	printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
-	return FALSE;
+	return false;
 }

drivers/block/sata_dwc.h

@@ -467,11 +467,4 @@ struct ata_port {
 	unsigned char		*pdata;
 };
 
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 #endif

drivers/block/sym53c8xx.c

@@ -764,9 +764,9 @@ int scsi_exec(ccb *pccb)
 retry:
 	scsi_issue(pccb);
 	if(pccb->contr_stat!=SIR_COMPLETE)
-		return FALSE;
+		return false;
 	if(pccb->status==S_GOOD)
-		return TRUE;
+		return true;
 	if(pccb->status==S_CHECK_COND) { /* check condition */
 		for(i=0;i<16;i++)
 			tmpcmd[i]=pccb->cmd[i];
@@ -797,12 +797,12 @@ retry:
 			case SENSE_NO_SENSE:
 			case SENSE_RECOVERED_ERROR:
 				/* seems to be ok */
-				return TRUE;
+				return true;
 				break;
 			case SENSE_NOT_READY:
 				if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
 					/* if device is not in process of becoming ready */
-					return FALSE;
+					return false;
 					break;
 				} /* else fall through */
 			case SENSE_UNIT_ATTENTION:
@@ -814,13 +814,13 @@ retry:
 					goto retry;
 				}
 				PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
-				return FALSE;
+				return false;
 			default:
-				return FALSE;
+				return false;
 		}
 	}
 	PRINTF("Status = %X\n",pccb->status);
-	return FALSE;
+	return false;
 }
 
 

drivers/fpga/ACEX1K.c

@@ -140,7 +140,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->config) (TRUE, TRUE, cookie);	/* Assert nCONFIG */
+		(*fn->config) (true, true, cookie);	/* Assert nCONFIG */
 
 		udelay(2);		/* T_cfg > 2us	*/
 
@@ -152,7 +152,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 			return FPGA_FAIL;
 		}
 
-		(*fn->config) (FALSE, TRUE, cookie);	/* Deassert nCONFIG */
+		(*fn->config) (false, true, cookie);	/* Deassert nCONFIG */
 		udelay(2);		/* T_cf2st1 < 4us	*/
 
 		/* Wait for nSTATUS to be released (i.e. deasserted) */
@@ -192,13 +192,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 			i = 8;
 			do {
 				/* Deassert the clock */
-				(*fn->clk) (FALSE, TRUE, cookie);
+				(*fn->clk) (false, true, cookie);
 				CONFIG_FPGA_DELAY ();
 				/* Write data */
-				(*fn->data) ( (val & 0x01), TRUE, cookie);
+				(*fn->data) ((val & 0x01), true, cookie);
 				CONFIG_FPGA_DELAY ();
 				/* Assert the clock */
-				(*fn->clk) (TRUE, TRUE, cookie);
+				(*fn->clk) (true, true, cookie);
 				CONFIG_FPGA_DELAY ();
 				val >>= 1;
 				i --;
@@ -232,9 +232,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 
 	for (i = 0; i < 12; i++) {
 		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 	}
 
 	ret_val = FPGA_SUCCESS;

drivers/fpga/altera.c

@@ -215,7 +215,7 @@ int altera_info( Altera_desc *desc )
 
 static int altera_validate (Altera_desc * desc, const char *fn)
 {
-	int ret_val = FALSE;
+	int ret_val = false;
 
 	if (desc) {
 		if ((desc->family > min_altera_type) &&
@@ -223,7 +223,7 @@ static int altera_validate (Altera_desc * desc, const char *fn)
 			if ((desc->iface > min_altera_iface_type) &&
 				(desc->iface < max_altera_iface_type)) {
 				if (desc->size) {
-					ret_val = TRUE;
+					ret_val = true;
 				} else {
 					printf ("%s: NULL part size\n", fn);
 				}

drivers/fpga/cyclon2.c

@@ -144,9 +144,9 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->config) (FALSE, TRUE, cookie);	/* De-assert nCONFIG */
+		(*fn->config) (false, true, cookie);	/* De-assert nCONFIG */
 		udelay(100);
-		(*fn->config) (TRUE, TRUE, cookie);	/* Assert nCONFIG */
+		(*fn->config) (true, true, cookie);	/* Assert nCONFIG */
 
 		udelay(2);		/* T_cfg > 2us	*/
 
@@ -164,7 +164,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		/* Get ready for the burn */
 		CONFIG_FPGA_DELAY ();
 
-		ret = (*fn->write) (buf, bsize, TRUE, cookie);
+		ret = (*fn->write) (buf, bsize, true, cookie);
 		if (ret) {
 			puts ("** Write failed.\n");
 			(*fn->abort) (cookie);

drivers/fpga/lattice.c

@@ -275,7 +275,7 @@ signed char ispVM(void)
 
 static int lattice_validate(Lattice_desc *desc, const char *fn)
 {
-	int ret_val = FALSE;
+	int ret_val = false;
 
 	if (desc) {
 		if ((desc->family > min_lattice_type) &&
@@ -283,7 +283,7 @@ static int lattice_validate(Lattice_desc *desc, const char *fn)
 			if ((desc->iface > min_lattice_iface_type) &&
 				(desc->iface < max_lattice_iface_type)) {
 				if (desc->size) {
-					ret_val = TRUE;
+					ret_val = true;
 				} else {
 					printf("%s: NULL part size\n", fn);
 				}

drivers/fpga/spartan2.c

@@ -162,11 +162,11 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */
+		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */
 
 		/* Get ready for the burn */
 		CONFIG_FPGA_DELAY ();
-		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */
+		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */
 
 		ts = get_timer (0);		/* get current time */
 		/* Now wait for INIT and BUSY to go high */
@@ -179,20 +179,20 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-		(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
+		(*fn->wr) (true, true, cookie); /* Assert write, commit */
-		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 		/* Load the data */
 		while (bytecount < bsize) {
 			/* XXX - do we check for an Ctrl-C press in here ??? */
 			/* XXX - Check the error bit? */
 
-			(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
+			(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 			ts = get_timer (0);	/* get current time */
@@ -201,9 +201,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 				 * make sure we aren't busy forever... */
 
 				CONFIG_FPGA_DELAY ();
-				(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+				(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 				CONFIG_FPGA_DELAY ();
-				(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
@@ -220,8 +220,8 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (FALSE, TRUE, cookie);	/* Deassert the chip select */
+		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
-		(*fn->wr) (FALSE, TRUE, cookie);	/* Deassert the write pin */
+		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
@@ -233,9 +233,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		while ((*fn->done) (cookie) == FPGA_FAIL) {
 
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
@@ -277,15 +277,15 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 		/* dump the data */
 		while (bytecount < bsize) {
 			/* XXX - do we check for an Ctrl-C press in here ??? */
 
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
@@ -293,9 +293,9 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 #endif
 		}
 
-		(*fn->cs) (FALSE, FALSE, cookie);	/* Deassert the chip select */
+		(*fn->cs) (false, false, cookie);	/* Deassert the chip select */
-		(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
@@ -351,7 +351,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */
+		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */
 
 		/* Wait for INIT state (init low)                            */
 		ts = get_timer (0);		/* get current time */
@@ -365,7 +365,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		/* Get ready for the burn */
 		CONFIG_FPGA_DELAY ();
-		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */
+		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */
 
 		ts = get_timer (0);		/* get current time */
 		/* Now wait for INIT to go high */
@@ -390,13 +390,13 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			i = 8;
 			do {
 				/* Deassert the clock */
-				(*fn->clk) (FALSE, TRUE, cookie);
+				(*fn->clk) (false, true, cookie);
 				CONFIG_FPGA_DELAY ();
 				/* Write data */
-				(*fn->wr) ((val & 0x80), TRUE, cookie);
+				(*fn->wr) ((val & 0x80), true, cookie);
 				CONFIG_FPGA_DELAY ();
 				/* Assert the clock */
-				(*fn->clk) (TRUE, TRUE, cookie);
+				(*fn->clk) (true, true, cookie);
 				CONFIG_FPGA_DELAY ();
 				val <<= 1;
 				i --;
@@ -417,14 +417,14 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		/* now check for done signal */
 		ts = get_timer (0);		/* get current time */
 		ret_val = FPGA_SUCCESS;
-		(*fn->wr) (TRUE, TRUE, cookie);
+		(*fn->wr) (true, true, cookie);
 
 		while (! (*fn->done) (cookie)) {
 
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 			putc ('*');
 

drivers/fpga/spartan3.c

@@ -166,11 +166,11 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */
+		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */
 
 		/* Get ready for the burn */
 		CONFIG_FPGA_DELAY ();
-		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */
+		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */
 
 		ts = get_timer (0);		/* get current time */
 		/* Now wait for INIT and BUSY to go high */
@@ -183,20 +183,20 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-		(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
+		(*fn->wr) (true, true, cookie); /* Assert write, commit */
-		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 		/* Load the data */
 		while (bytecount < bsize) {
 			/* XXX - do we check for an Ctrl-C press in here ??? */
 			/* XXX - Check the error bit? */
 
-			(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
+			(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 			ts = get_timer (0);	/* get current time */
@@ -205,9 +205,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 				 * make sure we aren't busy forever... */
 
 				CONFIG_FPGA_DELAY ();
-				(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+				(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 				CONFIG_FPGA_DELAY ();
-				(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
@@ -224,8 +224,8 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (FALSE, TRUE, cookie);	/* Deassert the chip select */
+		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
-		(*fn->wr) (FALSE, TRUE, cookie);	/* Deassert the write pin */
+		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
@@ -239,9 +239,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			 * make sure we aren't busy forever... */
 
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
@@ -283,15 +283,15 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
+		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 		/* dump the data */
 		while (bytecount < bsize) {
 			/* XXX - do we check for an Ctrl-C press in here ??? */
 
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
@@ -299,9 +299,9 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 #endif
 		}
 
-		(*fn->cs) (FALSE, FALSE, cookie);	/* Deassert the chip select */
+		(*fn->cs) (false, false, cookie);	/* Deassert the chip select */
-		(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
-		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
@@ -357,7 +357,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		/* Establish the initial state */
-		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */
+		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */
 
 		/* Wait for INIT state (init low)                            */
 		ts = get_timer (0);		/* get current time */
@@ -373,7 +373,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		/* Get ready for the burn */
 		CONFIG_FPGA_DELAY ();
-		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */
+		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */
 
 		ts = get_timer (0);		/* get current time */
 		/* Now wait for INIT to go high */
@@ -389,7 +389,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		/* Load the data */
 		if(*fn->bwr)
-			(*fn->bwr) (data, bsize, TRUE, cookie);
+			(*fn->bwr) (data, bsize, true, cookie);
 		else {
 			while (bytecount < bsize) {
 
@@ -405,13 +405,13 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 				i = 8;
 				do {
 					/* Deassert the clock */
-					(*fn->clk) (FALSE, TRUE, cookie);
+					(*fn->clk) (false, true, cookie);
 					CONFIG_FPGA_DELAY ();
 					/* Write data */
-					(*fn->wr) ((val & 0x80), TRUE, cookie);
+					(*fn->wr) ((val & 0x80), true, cookie);
 					CONFIG_FPGA_DELAY ();
 					/* Assert the clock */
-					(*fn->clk) (TRUE, TRUE, cookie);
+					(*fn->clk) (true, true, cookie);
 					CONFIG_FPGA_DELAY ();
 					val <<= 1;
 					i --;
@@ -433,16 +433,16 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		/* now check for done signal */
 		ts = get_timer (0);		/* get current time */
 		ret_val = FPGA_SUCCESS;
-		(*fn->wr) (TRUE, TRUE, cookie);
+		(*fn->wr) (true, true, cookie);
 
 		while (! (*fn->done) (cookie)) {
 			/* XXX - we should have a check in here somewhere to
 			 * make sure we aren't busy forever... */
 
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
 			putc ('*');
 

drivers/fpga/virtex2.c

@@ -221,7 +221,7 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		 * There is no maximum value for the pulse width.  Check to make
 		 * sure that INIT_B goes low after assertion of PROG_B
 		 */
-		(*fn->pgm) (TRUE, TRUE, cookie);
+		(*fn->pgm) (true, true, cookie);
 		udelay (10);
 		ts = get_timer (0);
 		do {
@@ -234,9 +234,9 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 		} while (!(*fn->init) (cookie));
 
-		(*fn->pgm) (FALSE, TRUE, cookie);
+		(*fn->pgm) (false, true, cookie);
 		CONFIG_FPGA_DELAY ();
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		/*
 		 * Start a timer and wait for INIT_B to go high
@@ -253,8 +253,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-		(*fn->wr) (TRUE, TRUE, cookie);
+		(*fn->wr) (true, true, cookie);
-		(*fn->cs) (TRUE, TRUE, cookie);
+		(*fn->cs) (true, true, cookie);
 
 		udelay (10000);
 
@@ -286,15 +286,15 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-			(*fn->wdata) (data[bytecount++], TRUE, cookie);
+			(*fn->wdata) (data[bytecount++], true, cookie);
 			CONFIG_FPGA_DELAY ();
 
 			/*
 			 * Cycle the clock pin
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
 			CONFIG_FPGA_DELAY ();
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 			ts = get_timer (0);
@@ -319,8 +319,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
 		 */
 		CONFIG_FPGA_DELAY ();
-		(*fn->cs) (FALSE, TRUE, cookie);
+		(*fn->cs) (false, true, cookie);
-		(*fn->wr) (FALSE, TRUE, cookie);
+		(*fn->wr) (false, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');
@@ -381,8 +381,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 		printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-		(*fn->cs) (TRUE, TRUE, cookie);
+		(*fn->cs) (true, true, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->clk) (true, true, cookie);
 
 		while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -394,8 +394,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 			/*
 			 * Cycle the clock and read the data
 			 */
-			(*fn->clk) (FALSE, TRUE, cookie);
+			(*fn->clk) (false, true, cookie);
-			(*fn->clk) (TRUE, TRUE, cookie);
+			(*fn->clk) (true, true, cookie);
 			(*fn->rdata) (&(data[bytecount++]), cookie);
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
@@ -406,9 +406,9 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 		/*
 		 * Deassert CS_B and cycle the clock to deselect the device.
 		 */
-		(*fn->cs) (FALSE, FALSE, cookie);
+		(*fn->cs) (false, false, cookie);
-		(*fn->clk) (FALSE, TRUE, cookie);
+		(*fn->clk) (false, true, cookie);
-		(*fn->clk) (TRUE, TRUE, cookie);
+		(*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc ('\n');

drivers/fpga/xilinx.c

@@ -242,7 +242,7 @@ int xilinx_info (Xilinx_desc * desc)
 
 static int xilinx_validate (Xilinx_desc * desc, char *fn)
 {
-	int ret_val = FALSE;
+	int ret_val = false;
 
 	if (desc) {
 		if ((desc->family > min_xilinx_type) &&
@@ -250,7 +250,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
 			if ((desc->iface > min_xilinx_iface_type) &&
 				(desc->iface < max_xilinx_iface_type)) {
 				if (desc->size) {
-					ret_val = TRUE;
+					ret_val = true;
 				} else
 					printf ("%s: NULL part size\n", fn);
 			} else

drivers/mtd/nand/mxc_nand.c

@@ -29,8 +29,6 @@
 
 #define DRIVER_NAME "mxc_nand"
 
-typedef enum {false, true} bool;
-
 struct mxc_nand_host {
 	struct mtd_info			mtd;
 	struct nand_chip		*nand;

drivers/net/armada100_fec.c

@@ -100,7 +100,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
 	}
 
 	/* wait for the SMI register to become available */
-	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
+	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
 		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
 		return -1;
 	}
@@ -108,7 +108,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
 	writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);
 
 	/* now wait for the data to be valid */
-	if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, TRUE)) {
+	if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) {
 		val = readl(&regs->smi);
 		printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
 				__func__, val);
@@ -143,7 +143,7 @@ static int smi_reg_write(const char *devname,
 	}
 
 	/* wait for the SMI register to become available */
-	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
+	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
 		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
 		return -1;
 	}

drivers/net/armada100_fec.h

@@ -29,13 +29,6 @@
 #ifndef __ARMADA100_FEC_H__
 #define __ARMADA100_FEC_H__
 
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
 #define PORT_NUM		0x0
 
 /* RX & TX descriptor command */

drivers/net/e1000.c

@@ -313,14 +313,14 @@ void e1000_standby_eeprom(struct e1000_hw *hw)
 *
 * hw - Struct containing variables accessed by shared code
 ****************************************************************************/
-static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
+static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 {
 	uint32_t eecd = 0;
 
 	DEBUGFUNC();
 
 	if (hw->mac_type == e1000_ich8lan)
-		return FALSE;
+		return false;
 
 	if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 		eecd = E1000_READ_REG(hw, EECD);
@@ -330,9 +330,9 @@ static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 
 		/* If both bits are set, device is Flash type */
 		if (eecd == 0x03)
-			return FALSE;
+			return false;
 	}
-	return TRUE;
+	return true;
 }
 
 /******************************************************************************
@@ -421,8 +421,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 		eeprom->opcode_bits = 3;
 		eeprom->address_bits = 6;
 		eeprom->delay_usec = 50;
-		eeprom->use_eerd = FALSE;
+		eeprom->use_eerd = false;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 	break;
 	case e1000_82540:
 	case e1000_82545:
@@ -439,8 +439,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 			eeprom->word_size = 64;
 			eeprom->address_bits = 6;
 		}
-		eeprom->use_eerd = FALSE;
+		eeprom->use_eerd = false;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 		break;
 	case e1000_82541:
 	case e1000_82541_rev_2:
@@ -469,8 +469,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 				eeprom->address_bits = 6;
 			}
 		}
-		eeprom->use_eerd = FALSE;
+		eeprom->use_eerd = false;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 		break;
 	case e1000_82571:
 	case e1000_82572:
@@ -484,8 +484,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 			eeprom->page_size = 8;
 			eeprom->address_bits = 8;
 		}
-		eeprom->use_eerd = FALSE;
+		eeprom->use_eerd = false;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 		break;
 	case e1000_82573:
 	case e1000_82574:
@@ -499,9 +499,9 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 			eeprom->page_size = 8;
 			eeprom->address_bits = 8;
 		}
-		eeprom->use_eerd = TRUE;
+		eeprom->use_eerd = true;
-		eeprom->use_eewr = TRUE;
+		eeprom->use_eewr = true;
-		if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+		if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 			eeprom->type = e1000_eeprom_flash;
 			eeprom->word_size = 2048;
 
@@ -522,8 +522,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 			eeprom->page_size = 8;
 			eeprom->address_bits = 8;
 		}
-		eeprom->use_eerd = TRUE;
+		eeprom->use_eerd = true;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 		break;
 
 	/* ich8lan does not support currently. if needed, please
@@ -535,8 +535,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 		int32_t  i = 0;
 
 		eeprom->type = e1000_eeprom_ich8;
-		eeprom->use_eerd = FALSE;
+		eeprom->use_eerd = false;
-		eeprom->use_eewr = FALSE;
+		eeprom->use_eewr = false;
 		eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 		uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 				ICH_FLASH_GFPREG);
@@ -544,7 +544,7 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 		 * so as to save time for driver init */
 		if (hw->eeprom_shadow_ram != NULL) {
 			for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-				hw->eeprom_shadow_ram[i].modified = FALSE;
+				hw->eeprom_shadow_ram[i].modified = false;
 				hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 			}
 		}
@@ -779,8 +779,8 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 	 * directly. In this case, we need to acquire the EEPROM so that
 	 * FW or other port software does not interrupt.
 	 */
-	if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
+	if (e1000_is_onboard_nvm_eeprom(hw) == true &&
-		hw->eeprom.use_eerd == FALSE) {
+		hw->eeprom.use_eerd == false) {
 
 		/* Prepare the EEPROM for bit-bang reading */
 		if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
@@ -788,7 +788,7 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 	}
 
 	/* Eerd register EEPROM access requires no eeprom aquire/release */
-	if (eeprom->use_eerd == TRUE)
+	if (eeprom->use_eerd == true)
 		return e1000_read_eeprom_eerd(hw, offset, words, data);
 
 	/* ich8lan does not support currently. if needed, please
@@ -935,7 +935,7 @@ e1000_set_phy_mode(struct e1000_hw *hw)
 			if (ret_val)
 				return ret_val;
 
-			hw->phy_reset_disable = FALSE;
+			hw->phy_reset_disable = false;
 		}
 	}
 
@@ -1098,17 +1098,17 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
 	return E1000_SUCCESS;
 }
 
-static boolean_t e1000_is_second_port(struct e1000_hw *hw)
+static bool e1000_is_second_port(struct e1000_hw *hw)
 {
 	switch (hw->mac_type) {
 	case e1000_80003es2lan:
 	case e1000_82546:
 	case e1000_82571:
 		if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
-			return TRUE;
+			return true;
 		/* Fallthrough */
 	default:
-		return FALSE;
+		return false;
 	}
 }
 
@@ -1373,7 +1373,7 @@ e1000_reset_hw(struct e1000_hw *hw)
 	E1000_WRITE_FLUSH(hw);
 
 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-	hw->tbi_compatibility_on = FALSE;
+	hw->tbi_compatibility_on = false;
 
 	/* Delay to allow any outstanding PCI transactions to complete before
 	 * resetting the device
@@ -2098,7 +2098,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
 		hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
 		hw->mac_type == e1000_82541_rev_2
 		|| hw->mac_type == e1000_82547_rev_2)
-			hw->phy_reset_disable = FALSE;
+			hw->phy_reset_disable = false;
 
 	return E1000_SUCCESS;
 }
@@ -2118,7 +2118,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
  ****************************************************************************/
 
 static int32_t
-e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
+e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
 {
 	uint32_t phy_ctrl = 0;
 	int32_t ret_val;
@@ -2253,7 +2253,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
  ****************************************************************************/
 
 static int32_t
-e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
+e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
 {
 	uint32_t phy_ctrl = 0;
 	int32_t ret_val;
@@ -2378,7 +2378,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
 	if (hw->phy_type == e1000_phy_igp) {
 		/* disable lplu d3 during driver init */
-		ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+		ret_val = e1000_set_d3_lplu_state(hw, false);
 		if (ret_val) {
 			DEBUGOUT("Error Disabling LPLU D3\n");
 			return ret_val;
@@ -2386,7 +2386,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
 	}
 
 	/* disable lplu d0 during driver init */
-	ret_val = e1000_set_d0_lplu_state(hw, FALSE);
+	ret_val = e1000_set_d0_lplu_state(hw, false);
 	if (ret_val) {
 		DEBUGOUT("Error Disabling LPLU D0\n");
 		return ret_val;
@@ -2495,9 +2495,9 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
 /*****************************************************************************
  * This function checks the mode of the firmware.
  *
- * returns  - TRUE when the mode is IAMT or FALSE.
+ * returns  - true when the mode is IAMT or false.
  ****************************************************************************/
-boolean_t
+bool
 e1000_check_mng_mode(struct e1000_hw *hw)
 {
 	uint32_t fwsm;
@@ -2508,12 +2508,12 @@ e1000_check_mng_mode(struct e1000_hw *hw)
 	if (hw->mac_type == e1000_ich8lan) {
 		if ((fwsm & E1000_FWSM_MODE_MASK) ==
 		    (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
-			return TRUE;
+			return true;
 	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
 		       (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
-			return TRUE;
+			return true;
 
-	return FALSE;
+	return false;
 }
 
 static int32_t
@@ -2675,7 +2675,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
 	 * firmware will have already initialized them.  We only initialize
 	 * them if the HW is not in IAMT mode.
 	 */
-		if (e1000_check_mng_mode(hw) == FALSE) {
+		if (e1000_check_mng_mode(hw) == false) {
 			/* Enable Electrical Idle on the PHY */
 			phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 			ret_val = e1000_write_phy_reg(hw,
@@ -2879,7 +2879,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
 		}
 	}
 
-	hw->get_link_status = TRUE;
+	hw->get_link_status = true;
 
 	return E1000_SUCCESS;
 }
@@ -3598,7 +3598,7 @@ e1000_check_for_link(struct eth_device *nic)
 		}
 
 		if (phy_data & MII_SR_LINK_STATUS) {
-			hw->get_link_status = FALSE;
+			hw->get_link_status = false;
 		} else {
 			/* No link detected */
 			return -E1000_ERR_NOLINK;
@@ -3661,7 +3661,7 @@ e1000_check_for_link(struct eth_device *nic)
 					rctl = E1000_READ_REG(hw, RCTL);
 					rctl &= ~E1000_RCTL_SBP;
 					E1000_WRITE_REG(hw, RCTL, rctl);
-					hw->tbi_compatibility_on = FALSE;
+					hw->tbi_compatibility_on = false;
 				}
 			} else {
 				/* If TBI compatibility is was previously off, turn it on. For
@@ -3670,7 +3670,7 @@ e1000_check_for_link(struct eth_device *nic)
 				 * will look like CRC errors to to the hardware.
 				 */
 				if (!hw->tbi_compatibility_on) {
-					hw->tbi_compatibility_on = TRUE;
+					hw->tbi_compatibility_on = true;
 					rctl = E1000_READ_REG(hw, RCTL);
 					rctl |= E1000_RCTL_SBP;
 					E1000_WRITE_REG(hw, RCTL, rctl);
@@ -4569,7 +4569,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
 {
 	int32_t phy_init_status, ret_val;
 	uint16_t phy_id_high, phy_id_low;
-	boolean_t match = FALSE;
+	bool match = false;
 
 	DEBUGFUNC();
 
@@ -4609,11 +4609,11 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
 	switch (hw->mac_type) {
 	case e1000_82543:
 		if (hw->phy_id == M88E1000_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_82544:
 		if (hw->phy_id == M88E1000_I_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_82540:
 	case e1000_82545:
@@ -4621,37 +4621,37 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
 	case e1000_82546:
 	case e1000_82546_rev_3:
 		if (hw->phy_id == M88E1011_I_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_82541:
 	case e1000_82541_rev_2:
 	case e1000_82547:
 	case e1000_82547_rev_2:
 		if(hw->phy_id == IGP01E1000_I_PHY_ID)
-			match = TRUE;
+			match = true;
 
 		break;
 	case e1000_82573:
 		if (hw->phy_id == M88E1111_I_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_82574:
 		if (hw->phy_id == BME1000_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_80003es2lan:
 		if (hw->phy_id == GG82563_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	case e1000_ich8lan:
 		if (hw->phy_id == IGP03E1000_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		if (hw->phy_id == IFE_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		if (hw->phy_id == IFE_PLUS_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		if (hw->phy_id == IFE_C_E_PHY_ID)
-			match = TRUE;
+			match = true;
 		break;
 	default:
 		DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
@@ -4682,7 +4682,7 @@ e1000_set_media_type(struct e1000_hw *hw)
 
 	if (hw->mac_type != e1000_82543) {
 		/* tbi_compatibility is only valid on 82543 */
-		hw->tbi_compatibility_en = FALSE;
+		hw->tbi_compatibility_en = false;
 	}
 
 	switch (hw->device_id) {
@@ -4714,7 +4714,7 @@ e1000_set_media_type(struct e1000_hw *hw)
 			if (status & E1000_STATUS_TBIMODE) {
 				hw->media_type = e1000_media_type_fiber;
 				/* tbi_compatibility not valid on fiber */
-				hw->tbi_compatibility_en = FALSE;
+				hw->tbi_compatibility_en = false;
 			} else {
 				hw->media_type = e1000_media_type_copper;
 			}
@@ -4788,8 +4788,8 @@ e1000_sw_init(struct eth_device *nic)
 		hw->media_type = e1000_media_type_fiber;
 	}
 
-	hw->tbi_compatibility_en = TRUE;
+	hw->tbi_compatibility_en = true;
-	hw->wait_autoneg_complete = TRUE;
+	hw->wait_autoneg_complete = true;
 	if (hw->mac_type < e1000_82543)
 		hw->report_tx_early = 0;
 	else
@@ -5194,7 +5194,7 @@ e1000_initialize(bd_t * bis)
 		hw->original_fc = e1000_fc_default;
 		hw->autoneg_failed = 0;
 		hw->autoneg = 1;
-		hw->get_link_status = TRUE;
+		hw->get_link_status = true;
 		hw->hw_addr = pci_map_bar(devno,	PCI_BASE_ADDRESS_0,
 							PCI_REGION_MEM);
 		hw->mac_type = e1000_undefined;

drivers/net/e1000.h

@@ -89,11 +89,6 @@ int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 		int argc, char * const argv[]);
 #endif
 
-typedef enum {
-	FALSE = 0,
-	TRUE = 1
-} boolean_t;
-
 /* Enumerated types specific to the e1000 hardware */
 /* Media Access Controlers */
 typedef enum {
@@ -340,7 +335,7 @@ struct e1000_phy_stats {
 						   Control and Address */
 #define IFE_PHY_SPECIAL_CONTROL           0x11  /* 100BaseTx PHY special
 						   control register */
-#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive False
+#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive false
 						   Carrier Counter */
 #define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnet
 						   Counter */
@@ -1040,14 +1035,14 @@ struct e1000_hw_stats {
 };
 
 struct e1000_eeprom_info {
-    e1000_eeprom_type type;
+e1000_eeprom_type type;
-    uint16_t word_size;
+	uint16_t word_size;
-    uint16_t opcode_bits;
+	uint16_t opcode_bits;
-    uint16_t address_bits;
+	uint16_t address_bits;
-    uint16_t delay_usec;
+	uint16_t delay_usec;
-    uint16_t page_size;
+	uint16_t page_size;
-    boolean_t use_eerd;
+	bool use_eerd;
-    boolean_t use_eewr;
+	bool use_eewr;
 };
 
 typedef enum {
@@ -1150,20 +1145,20 @@ struct e1000_hw {
 #if 0
 	uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
 #endif
-	boolean_t disable_polarity_correction;
+	bool disable_polarity_correction;
-	boolean_t		speed_downgraded;
+	bool		speed_downgraded;
-	boolean_t get_link_status;
+	bool get_link_status;
-	boolean_t tbi_compatibility_en;
+	bool tbi_compatibility_en;
-	boolean_t tbi_compatibility_on;
+	bool tbi_compatibility_on;
-	boolean_t		fc_strict_ieee;
+	bool		fc_strict_ieee;
-	boolean_t fc_send_xon;
+	bool fc_send_xon;
-	boolean_t report_tx_early;
+	bool report_tx_early;
-	boolean_t phy_reset_disable;
+	bool phy_reset_disable;
-	boolean_t		initialize_hw_bits_disable;
+	bool		initialize_hw_bits_disable;
 #if 0
-	boolean_t adaptive_ifs;
+	bool adaptive_ifs;
-	boolean_t ifs_params_forced;
+	bool ifs_params_forced;
-	boolean_t in_ifs_mode;
+	bool in_ifs_mode;
 #endif
 	e1000_smart_speed	smart_speed;
 	e1000_dsp_config	dsp_config_state;
@@ -1860,11 +1855,11 @@ struct e1000_hw {
  * Typical use:
  *  ...
  *  if (TBI_ACCEPT) {
- *	accept_frame = TRUE;
+ *	accept_frame = true;
  *	e1000_tbi_adjust_stats(adapter, MacAddress);
  *	frame_length--;
  *  } else {
- *	accept_frame = FALSE;
+ *	accept_frame = false;
  *  }
  *  ...
  */
@@ -2080,7 +2075,7 @@ struct e1000_hw {
 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT   0x0020 /* 1=Downshift Detected */
 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE  0x0040 /* 1=Crossover Changed */
-#define GG82563_PSSR2_FALSE_CARRIER         0x0100 /* 1=False Carrier */
+#define GG82563_PSSR2_FALSE_CARRIER         0x0100 /* 1=false Carrier */
 #define GG82563_PSSR2_SYMBOL_ERROR          0x0200 /* 1=Symbol Error */
 #define GG82563_PSSR2_LINK_STATUS_CHANGED   0x0400 /* 1=Link Status Changed */
 #define GG82563_PSSR2_AUTO_NEG_COMPLETED    0x0800 /* 1=Auto-Neg Completed */

drivers/net/e1000_spi.c

@@ -17,7 +17,7 @@
  * never return an error.
  */
 static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen,
-		const void *dout_mem, void *din_mem, boolean_t intr)
+		const void *dout_mem, void *din_mem, bool intr)
 {
 	const uint8_t *dout = dout_mem;
 	uint8_t *din = din_mem;
@@ -145,7 +145,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen,
 	if (flags & SPI_XFER_BEGIN)
 		e1000_standby_eeprom(hw);
 
-	ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, TRUE);
+	ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, true);
 
 	if (flags & SPI_XFER_END)
 		e1000_standby_eeprom(hw);
@@ -169,7 +169,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen,
 #define SPI_EEPROM_STATUS_BUSY	0x01
 #define SPI_EEPROM_STATUS_WREN	0x02
 
-static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr)
 {
 	u8 op[] = { SPI_EEPROM_ENABLE_WR };
 	e1000_standby_eeprom(hw);
@@ -181,7 +181,7 @@ static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr)
  * of the EEPROM commands at this time.
  */
 #if 0
-static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr)
 {
 	u8 op[] = { SPI_EEPROM_DISABLE_WR };
 	e1000_standby_eeprom(hw);
@@ -189,7 +189,7 @@ static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr)
 }
 
 static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
-		u8 status, boolean_t intr)
+		u8 status, bool intr)
 {
 	u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
 	e1000_standby_eeprom(hw);
@@ -197,7 +197,7 @@ static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
 }
 #endif
 
-static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr)
 {
 	u8 op[] = { SPI_EEPROM_READ_STATUS, 0 };
 	e1000_standby_eeprom(hw);
@@ -207,7 +207,7 @@ static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr)
 }
 
 static int e1000_spi_eeprom_write_page(struct e1000_hw *hw,
-		const void *data, u16 off, u16 len, boolean_t intr)
+		const void *data, u16 off, u16 len, bool intr)
 {
 	u8 op[] = {
 		SPI_EEPROM_WRITE_PAGE,
@@ -225,7 +225,7 @@ static int e1000_spi_eeprom_write_page(struct e1000_hw *hw,
 }
 
 static int e1000_spi_eeprom_read_page(struct e1000_hw *hw,
-		void *data, u16 off, u16 len, boolean_t intr)
+		void *data, u16 off, u16 len, bool intr)
 {
 	u8 op[] = {
 		SPI_EEPROM_READ_PAGE,
@@ -242,7 +242,7 @@ static int e1000_spi_eeprom_read_page(struct e1000_hw *hw,
 	return 0;
 }
 
-static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr)
 {
 	int status;
 	while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) {
@@ -253,7 +253,7 @@ static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr)
 }
 
 static int e1000_spi_eeprom_dump(struct e1000_hw *hw,
-		void *data, u16 off, unsigned int len, boolean_t intr)
+		void *data, u16 off, unsigned int len, bool intr)
 {
 	/* Interruptibly wait for the EEPROM to be ready */
 	if (e1000_spi_eeprom_poll_ready(hw, intr))
@@ -282,7 +282,7 @@ static int e1000_spi_eeprom_dump(struct e1000_hw *hw,
 }
 
 static int e1000_spi_eeprom_program(struct e1000_hw *hw,
-		const void *data, u16 off, u16 len, boolean_t intr)
+		const void *data, u16 off, u16 len, bool intr)
 {
 	/* Program each page in sequence */
 	while (len) {
@@ -362,7 +362,7 @@ static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 		free(buffer);
 		return 1;
 	}
-	err = e1000_spi_eeprom_dump(hw, buffer, offset, length, TRUE);
+	err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true);
 	e1000_release_eeprom(hw);
 	if (err) {
 		E1000_ERR(hw->nic, "Interrupted!\n");
@@ -421,7 +421,7 @@ static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 	}
 
 	/* Perform the programming operation */
-	if (e1000_spi_eeprom_dump(hw, dest, offset, length, TRUE) < 0) {
+	if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) {
 		E1000_ERR(hw->nic, "Interrupted!\n");
 		e1000_release_eeprom(hw);
 		return 1;
@@ -456,7 +456,7 @@ static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 	}
 
 	/* Perform the programming operation */
-	if (e1000_spi_eeprom_program(hw, source, offset, length, TRUE) < 0) {
+	if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) {
 		E1000_ERR(hw->nic, "Interrupted!\n");
 		e1000_release_eeprom(hw);
 		return 1;
@@ -472,7 +472,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 {
 	uint16_t i, length, checksum = 0, checksum_reg;
 	uint16_t *buffer;
-	boolean_t upd;
+	bool upd;
 
 	if (argc == 0)
 		upd = 0;
@@ -498,7 +498,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 	}
 
 	/* Read the EEPROM */
-	if (e1000_spi_eeprom_dump(hw, buffer, 0, length, TRUE) < 0) {
+	if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) {
 		E1000_ERR(hw->nic, "Interrupted!\n");
 		e1000_release_eeprom(hw);
 		return 1;
@@ -533,7 +533,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
 	printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name);
 	buffer[i] = cpu_to_le16(checksum);
 	if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t),
-			sizeof(uint16_t), TRUE)) {
+			sizeof(uint16_t), true)) {
 		E1000_ERR(hw->nic, "Interrupted!\n");
 		e1000_release_eeprom(hw);
 		return 1;

drivers/net/ne2000_base.h

@@ -79,10 +79,6 @@ are GPL, so this is, of course, GPL.
 #ifndef __NE2000_BASE_H__
 #define __NE2000_BASE_H__
 
-#define bool int
-#define false 0
-#define true 1
-
 /*
  * Debugging details
  *

drivers/net/npe/IxEthAcc.c

@@ -82,7 +82,7 @@ extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
  * @ingroup IxEthAccPri
  *
  */
-BOOL ixEthAccServiceInit = FALSE;
+BOOL ixEthAccServiceInit = false;
 
 /* global filtering bit mask */
 PUBLIC UINT32 ixEthAccNewSrcMask;
@@ -168,7 +168,7 @@ PUBLIC IxEthAccStatus ixEthAccInit()
    }
 
    /* initialiasation is complete */
-   ixEthAccServiceInit = TRUE;
+   ixEthAccServiceInit = true;
 
    return IX_ETH_ACC_SUCCESS;
 
@@ -200,11 +200,11 @@ PUBLIC void ixEthAccUnload(void)
        /* set all ports as uninitialized */
        for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
        {
-	       ixEthAccPortData[portId].portInitialized = FALSE;
+	       ixEthAccPortData[portId].portInitialized = false;
        }
 
        /* uninitialize the service */
-       ixEthAccServiceInit = FALSE;
+       ixEthAccServiceInit = false;
    }
 }
 
@@ -248,7 +248,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
      * Set the port init flag.
      */
 
-    ixEthAccPortData[portId].portInitialized = TRUE;
+    ixEthAccPortData[portId].portInitialized = true;
 
 #ifdef CONFIG_IXP425_COMPONENT_ETHDB
     /* init learning/filtering database structures for this port */

drivers/net/npe/IxEthAccCommon.c

@@ -102,7 +102,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
+    true,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
@@ -122,7 +122,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
     IX_QMGR_Q_SIZE64,		     /**< Allocate Smaller Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
+    true,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
@@ -144,7 +144,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     (IxQMgrCallbackId) IX_ETH_PORT_1,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
+    false,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /***< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
@@ -157,7 +157,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     (IxQMgrCallbackId) IX_ETH_PORT_2,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
+    false,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
@@ -170,7 +170,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     (IxQMgrCallbackId) IX_ETH_PORT_3,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
+    false,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
@@ -183,7 +183,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
      (IxQMgrCallbackId) IX_ETH_PORT_1,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
+    false,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
@@ -196,7 +196,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
      (IxQMgrCallbackId) IX_ETH_PORT_2,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    FALSE,			     /**< Disable Q notification at startup */
+    false,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
@@ -209,7 +209,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
      (IxQMgrCallbackId) IX_ETH_PORT_3,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */
-    FALSE,			     /** Disable Q notification at startup */
+    false,			     /** Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /* No queues use almost empty */
     IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */
@@ -222,7 +222,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
      (IxQMgrCallbackId) 0,
     IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    TRUE,			     /**< Enable Q notification at startup */
+    true,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */
     IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */
@@ -449,7 +449,7 @@ ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
     /*
      * Set notification condition for Q
      */
-    if ( qInfoDes->qNotificationEnableAtStartup == TRUE )
+    if (qInfoDes->qNotificationEnableAtStartup == true)
     {
 	if (   ixQMgrNotificationEnable(qInfoDes->qId,
 					qInfoDes->qConditionSource)
@@ -513,7 +513,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
     IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
     IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
     UINT32 ixEthDBParameter = 0;
-    BOOL completelySorted = FALSE;
+    BOOL completelySorted = false;
 
     /* Fill the corspondance between ports and queues
      * This defines the mapping from port to queue Ids.
@@ -706,7 +706,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
     do
     {
 	sortIterations++;
-	completelySorted = TRUE;
+	completelySorted = true;
 	for (rxQueue = 0;
 	     rxQueue < rxQueueCount - sortIterations;
 	     rxQueue++)
@@ -732,7 +732,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
 		rxQueues[rxQueue+1].npeId = npeId;
 		rxQueues[rxQueue+1].qId = qId;
 		rxQueues[rxQueue+1].trafficClass = trafficClass;
-		completelySorted = FALSE;
+		completelySorted = false;
 	    }
 	}
     }

drivers/net/npe/IxEthAccDataPlane.c

@@ -948,7 +948,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
 	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
 	{
 	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE))
+		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
 	    {
 		/* one of the active ports has a different rx callback type.
 		 * Changing the callback type when the port is enabled
@@ -977,7 +977,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
 	return (IX_ETH_ACC_INVALID_ARG);
     }
 
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE;
+    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
 
     return (IX_ETH_ACC_SUCCESS);
 }
@@ -1025,7 +1025,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
 	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
 	{
 	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE))
+		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
 	    {
 		/* one of the active ports has a different rx callback type.
 		 * Changing the callback type when the port is enabled
@@ -1055,7 +1055,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
 	return (IX_ETH_ACC_INVALID_ARG);
     }
 
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE;
+    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
 
     return (IX_ETH_ACC_SUCCESS);
 }
@@ -1456,7 +1456,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
 	IX_ETH_ACC_FATAL_LOG(
 	     "ixEthRxFrameProcess: Illegal port: %u\n",
 	     (UINT32)portId, 0, 0, 0, 0, 0);
-	return FALSE;
+	return false;
     }
 #endif
 
@@ -1468,7 +1468,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
     if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
     {
 	/* "best case" scenario : nothing special to do for this frame */
-	return TRUE;
+	return true;
     }
 
 #ifdef CONFIG_IXP425_COMPONENT_ETHDB
@@ -1540,10 +1540,10 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
         RX_STATS_INC(portId, rxFiltered);
 
         /* indicate that frame should not be subjected to further processing */
-        return FALSE;
+        return false;
     }
 
-    return TRUE;
+    return true;
 }
 
 

drivers/net/npe/IxEthAccMac.c

@@ -304,7 +304,7 @@ ixEthAccPortEnablePriv(IxEthAccPortId portId)
 
     /* set the global state */
     ixEthAccMacState[portId].portDisableState = ACTIVE;
-    ixEthAccMacState[portId].enabled = TRUE;
+    ixEthAccMacState[portId].enabled = true;
 
     /* rewrite the setup (including mac filtering) depending
      * on current options
@@ -515,7 +515,7 @@ ixEthAccPortDisableRxCallback (UINT32 cbTag,
     IxEthAccPortId portId = (IxEthAccPortId)cbTag;
 
     /* call the portDisable receive callback */
-   (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE);
+   (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false);
 }
 
 PRIVATE void
@@ -527,7 +527,7 @@ ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
     while (*mBufPtr)
     {
 	/* call the portDisable receive callback with one buffer at a time */
-	(ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE);
+	(ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true);
     }
 }
 
@@ -820,7 +820,7 @@ ixEthAccPortDisablePriv(IxEthAccPortId portId)
     }
 
     /* disable MAC Tx and Rx services */
-    ixEthAccMacState[portId].enabled = FALSE;
+    ixEthAccMacState[portId].enabled = false;
     ixEthAccMacStateUpdate(portId);
 
     /* restore the Rx and TxDone callbacks (within a critical section) */
@@ -869,14 +869,14 @@ ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
         IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
 
         /* Since Eth NPE is not available, port must be disabled */
-        *enabled = FALSE ;
+        *enabled = false ;
         return IX_ETH_ACC_SUCCESS ;
     }
 
     if (!IX_ETH_IS_PORT_INITIALIZED(portId))
     {
         /* Since Eth NPE is not available, port must be disabled */
-        *enabled = FALSE ;
+        *enabled = false ;
 	return (IX_ETH_ACC_PORT_UNINITIALIZED);
     }
 
@@ -1259,7 +1259,7 @@ ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_RX_CNTRL1,
 	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
 
-    ixEthAccMacState[portId].promiscuous = FALSE;
+    ixEthAccMacState[portId].promiscuous = false;
 
     ixEthAccMulticastAddressSet(portId);
 
@@ -1297,7 +1297,7 @@ ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_RX_CNTRL1,
 	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
 
-    ixEthAccMacState[portId].promiscuous = TRUE;
+    ixEthAccMacState[portId].promiscuous = true;
 
     ixEthAccMulticastAddressSet(portId);
 
@@ -1361,7 +1361,7 @@ ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
 		  IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
 		  macAddr->macAddress[i]);
     }
-    ixEthAccMacState[portId].initDone = TRUE;
+    ixEthAccMacState[portId].initDone = true;
 
     return IX_ETH_ACC_SUCCESS;
 }
@@ -1552,7 +1552,7 @@ ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
 	   IX_IEEE803_MAC_ADDRESS_SIZE);
 
     ixEthAccMacState[portId].mcastAddrIndex = 1;
-    ixEthAccMacState[portId].joinAll = TRUE;
+    ixEthAccMacState[portId].joinAll = true;
 
     ixEthAccMulticastAddressSet(portId);
 
@@ -1599,7 +1599,7 @@ ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
 	{
 	    if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
 	    {
-		ixEthAccMacState[portId].joinAll = FALSE;
+		ixEthAccMacState[portId].joinAll = false;
 	    }
 	    /*Decrement the index into the multicast address table
 	      for the current port*/
@@ -1643,7 +1643,7 @@ ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
     }
 
     ixEthAccMacState[portId].mcastAddrIndex = 0;
-    ixEthAccMacState[portId].joinAll = FALSE;
+    ixEthAccMacState[portId].joinAll = false;
 
     ixEthAccMulticastAddressSet(portId);
 
@@ -1770,7 +1770,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
 	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_RX_CNTRL1,
 		  rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-	ixEthAccMacState[portId].fullDuplex = TRUE;
+	ixEthAccMacState[portId].fullDuplex = true;
 
     }
     else if (mode ==  IX_ETH_ACC_HALF_DUPLEX)
@@ -1786,7 +1786,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
 		  IX_ETH_ACC_MAC_RX_CNTRL1,
 		  rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
 
-	ixEthAccMacState[portId].fullDuplex = FALSE;
+	ixEthAccMacState[portId].fullDuplex = false;
     }
     else
     {
@@ -1876,7 +1876,7 @@ ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
 	      regval |
 	      IX_ETH_ACC_TX_CNTRL1_PAD_EN);
 
-    ixEthAccMacState[portId].txPADAppend = TRUE;
+    ixEthAccMacState[portId].txPADAppend = true;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -1908,7 +1908,7 @@ ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_TX_CNTRL1,
 	      regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
 
-    ixEthAccMacState[portId].txPADAppend = FALSE;
+    ixEthAccMacState[portId].txPADAppend = false;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -1941,7 +1941,7 @@ ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_TX_CNTRL1,
 	      regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
 
-    ixEthAccMacState[portId].txFCSAppend = TRUE;
+    ixEthAccMacState[portId].txFCSAppend = true;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -1973,7 +1973,7 @@ ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_TX_CNTRL1,
 	      regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
 
-    ixEthAccMacState[portId].txFCSAppend = FALSE;
+    ixEthAccMacState[portId].txFCSAppend = false;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -2004,7 +2004,7 @@ ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_RX_CNTRL1,
 	      regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
 
-    ixEthAccMacState[portId].rxFCSAppend = TRUE;
+    ixEthAccMacState[portId].rxFCSAppend = true;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -2035,7 +2035,7 @@ ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
 	      IX_ETH_ACC_MAC_RX_CNTRL1,
 	      regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
 
-    ixEthAccMacState[portId].rxFCSAppend = FALSE;
+    ixEthAccMacState[portId].rxFCSAppend = false;
     return IX_ETH_ACC_SUCCESS;
 }
 
@@ -2327,17 +2327,17 @@ ixEthAccMacInit(IxEthAccPortId portId)
         return IX_ETH_ACC_SUCCESS ;
     }
 
-    if(ixEthAccMacState[portId].macInitialised == FALSE)
+    if(ixEthAccMacState[portId].macInitialised == false)
     {
-	ixEthAccMacState[portId].fullDuplex  = TRUE;
+	ixEthAccMacState[portId].fullDuplex  = true;
-	ixEthAccMacState[portId].rxFCSAppend = TRUE;
+	ixEthAccMacState[portId].rxFCSAppend = true;
-	ixEthAccMacState[portId].txFCSAppend = TRUE;
+	ixEthAccMacState[portId].txFCSAppend = true;
-	ixEthAccMacState[portId].txPADAppend = TRUE;
+	ixEthAccMacState[portId].txPADAppend = true;
-	ixEthAccMacState[portId].enabled     = FALSE;
+	ixEthAccMacState[portId].enabled     = false;
-	ixEthAccMacState[portId].promiscuous = TRUE;
+	ixEthAccMacState[portId].promiscuous = true;
-	ixEthAccMacState[portId].joinAll     = FALSE;
+	ixEthAccMacState[portId].joinAll     = false;
-	ixEthAccMacState[portId].initDone    = FALSE;
+	ixEthAccMacState[portId].initDone    = false;
-	ixEthAccMacState[portId].macInitialised = TRUE;
+	ixEthAccMacState[portId].macInitialised = true;
 
         /* initialize MIB stats mutexes */
         ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
@@ -2417,7 +2417,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
 {
     UINT32 regval;
 
-    if ( ixEthAccMacState[portId].enabled == FALSE )
+    if ( ixEthAccMacState[portId].enabled == false )
     {
 	/*  Just disable both the transmitter and reciver in the MAC.  */
         REG_READ(ixEthAccMacBase[portId],
@@ -2480,7 +2480,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
 	ixEthAccPortPromiscuousModeClearPriv(portId);
     }
 
-    if ( ixEthAccMacState[portId].enabled == TRUE )
+    if ( ixEthAccMacState[portId].enabled == true )
     {
         /*   Enable both the transmitter and reciver in the MAC.  */
         REG_READ(ixEthAccMacBase[portId],
@@ -2509,10 +2509,10 @@ ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
     {
 	if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
 	{
-	    return FALSE;
+	    return false;
 	}
     }
-    return TRUE;
+    return true;
 }
 
 PRIVATE void
@@ -2554,7 +2554,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId)
      * are set in the result
      */
 
-    if (ixEthAccMacState[portId].promiscuous == TRUE)
+    if (ixEthAccMacState[portId].promiscuous == true)
     {
 	/* Promiscuous Mode is set, and filtering
 	 * allow all packets, and enable the mcast and
@@ -2569,7 +2569,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId)
     }
     else
     {
-	if(ixEthAccMacState[portId].joinAll == TRUE)
+	if(ixEthAccMacState[portId].joinAll == true)
 	{
 	    /* Join all is set. The mask and address are
 	     * the multicast settings.

drivers/net/npe/IxEthDBAPI.c

@@ -60,7 +60,7 @@ IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDB
     
     IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
 
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE);
+    return ixEthDBTriggerAddPortUpdate(macAddr, portID, true);
 }
     
 IX_ETH_DB_PUBLIC
@@ -74,7 +74,7 @@ IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthD
 
     IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
 
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE);
+    return ixEthDBTriggerAddPortUpdate(macAddr, portID, false);
 }
 
 IX_ETH_DB_PUBLIC
@@ -102,7 +102,7 @@ void ixEthDBDatabaseMaintenance()
 {
     HashIterator iterator;
     UINT32 portIndex;
-    BOOL agingRequired = FALSE;
+    BOOL agingRequired = false;
 
     /* ports who will have deleted records and therefore will need updating */
     IxEthDBPortMap triggerPorts;
@@ -120,7 +120,7 @@ void ixEthDBDatabaseMaintenance()
     {
         if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
         {
-            agingRequired = TRUE;
+            agingRequired = true;
         }
     }
 
@@ -152,9 +152,9 @@ void ixEthDBDatabaseMaintenance()
                 }
                 else
                 {
-                    ixEthDBPortInfo[portIndex].agingEnabled                = FALSE;
+                    ixEthDBPortInfo[portIndex].agingEnabled                = false;
-                    ixEthDBPortInfo[portIndex].updateMethod.updateEnabled  = FALSE;
+                    ixEthDBPortInfo[portIndex].updateMethod.updateEnabled  = false;
-                    ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE;
+                    ixEthDBPortInfo[portIndex].updateMethod.userControlled = true;
 
                     ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
                         IX_OSAL_LOG_DEV_STDOUT, 
@@ -173,7 +173,7 @@ void ixEthDBDatabaseMaintenance()
         {
             MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
             UINT32 *age               = NULL;
-            BOOL staticEntry          = TRUE;
+            BOOL staticEntry          = true;
 
             if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
             {
@@ -187,10 +187,10 @@ void ixEthDBDatabaseMaintenance()
             }
             else
             {
-                staticEntry = TRUE;
+                staticEntry = true;
             }
 
-            if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE))
+            if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false))
             {
                 /* manually increment the age if the port has no such capability */
                 if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
@@ -341,7 +341,7 @@ IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
 
     IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
 
-    ixEthDBPortInfo[portID].agingEnabled = FALSE;
+    ixEthDBPortInfo[portID].agingEnabled = false;
 
     return IX_ETH_DB_SUCCESS;
 }
@@ -355,7 +355,7 @@ IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
 
     IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
 
-    ixEthDBPortInfo[portID].agingEnabled = TRUE;
+    ixEthDBPortInfo[portID].agingEnabled = true;
 
     return IX_ETH_DB_SUCCESS;
 }
@@ -442,7 +442,7 @@ IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate
     IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
 
     ixEthDBPortInfo[portID].updateMethod.updateEnabled  = enableUpdate;
-    ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
+    ixEthDBPortInfo[portID].updateMethod.userControlled = true;
 
     return IX_ETH_DB_SUCCESS;
 }

drivers/net/npe/IxEthDBAPISupport.c

@@ -128,18 +128,18 @@ void ixEthDBPortInit(IxEthDBPortId portID)
     SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
 
     /* default values */
-    portInfo->agingEnabled       = FALSE;
+    portInfo->agingEnabled       = false;
-    portInfo->enabled            = FALSE;
+    portInfo->enabled            = false;
-    portInfo->macAddressUploaded = FALSE;
+    portInfo->macAddressUploaded = false;
     portInfo->maxRxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
     portInfo->maxTxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
 
     /* default update control values */
     portInfo->updateMethod.searchTree              = NULL;
-    portInfo->updateMethod.searchTreePendingWrite  = FALSE;
+    portInfo->updateMethod.searchTreePendingWrite  = false;
-    portInfo->updateMethod.treeInitialized         = FALSE;
+    portInfo->updateMethod.treeInitialized         = false;
-    portInfo->updateMethod.updateEnabled           = FALSE;
+    portInfo->updateMethod.updateEnabled           = false;
-    portInfo->updateMethod.userControlled          = FALSE;
+    portInfo->updateMethod.userControlled          = false;
 
     /* default WiFi parameters */
     memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
@@ -153,9 +153,9 @@ void ixEthDBPortInit(IxEthDBPortId portID)
     }
 
     /* initialize state save */
-    ixEthDBPortState[portID].saved = FALSE;
+    ixEthDBPortState[portID].saved = false;
 
-    portInfo->initialized = TRUE;
+    portInfo->initialized = true;
 }
 
 /**
@@ -190,7 +190,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
     SET_DEPENDENCY_MAP(triggerPorts, portID);
 
     /* mark as enabled */
-    portInfo->enabled = TRUE;
+    portInfo->enabled = true;
 
     /* Operation stops here when Ethernet Learning is not enabled */
     if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
@@ -214,7 +214,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
         if (!portInfo->updateMethod.userControlled
                 && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
         {
-            portInfo->updateMethod.updateEnabled = TRUE;
+            portInfo->updateMethod.updateEnabled = true;
         }
 
         /* if this is first time initialization then we already have
@@ -227,7 +227,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
             ixEthDBUpdatePortLearningTrees(triggerPorts);
 
             /* mark tree as being initialized */
-            portInfo->updateMethod.treeInitialized = TRUE;
+            portInfo->updateMethod.treeInitialized = true;
         }
     }
 
@@ -262,7 +262,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
         ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
 
         /* discard previous save */
-        ixEthDBPortState[portID].saved = FALSE;
+        ixEthDBPortState[portID].saved = false;
     }
 
     IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
@@ -321,7 +321,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
         memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
         memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
 
-        ixEthDBPortState[portID].saved = TRUE;
+        ixEthDBPortState[portID].saved = true;
 
         /* now turn off all EthDB filtering features on the port */
 
@@ -330,7 +330,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
         if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
         {
             ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-            ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE);
+            ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false);
             ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
             ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
 
@@ -342,7 +342,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
         /* STP */
         if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
         {
-            ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE);
+            ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false);
         }
 
         /* Firewall */
@@ -350,7 +350,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
         {
             ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
             ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
-            ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE);
+            ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false);
         }
 
         /* Frame size filter */
@@ -413,18 +413,18 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
     }
 
     /* mark as disabled */
-    portInfo->enabled = FALSE;
+    portInfo->enabled = false;
 
     /* disable updates unless the user has specifically altered the default behavior */
     if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
     {
         if (!portInfo->updateMethod.userControlled)
         {
-            portInfo->updateMethod.updateEnabled = FALSE;
+            portInfo->updateMethod.updateEnabled = false;
         }
 
         /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
-        portInfo->updateMethod.treeInitialized = FALSE;
+        portInfo->updateMethod.treeInitialized = false;
     }
 
     ixEthDBUpdateUnlock();
@@ -668,7 +668,7 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd
 
     if (result == IX_SUCCESS)
     {
-        ixEthDBPortInfo[portID].macAddressUploaded = TRUE;
+        ixEthDBPortInfo[portID].macAddressUploaded = true;
     }
 
     return result;

drivers/net/npe/IxEthDBCore.c

@@ -51,7 +51,7 @@ IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX
 IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
 
 /* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE;
+IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false;
 
 /**
  * @brief initializes EthDB
@@ -124,7 +124,7 @@ IxEthDBStatus ixEthDBInit(void)
         ixEthDBFeatureCapabilityScan();
     }
 
-    ethDBInitializationComplete = TRUE;
+    ethDBInitializationComplete = true;
 
     return result;
 }
@@ -179,7 +179,7 @@ IxEthDBStatus ixEthDBUnload(void)
             ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
         }
 
-        ixEthDBPortInfo[portIndex].initialized = FALSE;
+        ixEthDBPortInfo[portIndex].initialized = false;
     }
 
     /* shutdown event processor */
@@ -188,7 +188,7 @@ IxEthDBStatus ixEthDBUnload(void)
     /* deallocate NPE update zones */
     ixEthDBNPEUpdateAreasUnload();
 
-    ethDBInitializationComplete = FALSE;
+    ethDBInitializationComplete = false;
 
     return IX_ETH_DB_SUCCESS;
 }

drivers/net/npe/IxEthDBEvents.c

@@ -61,8 +61,8 @@ IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
 IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
 IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
 
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown      = FALSE;
+IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown      = false;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE;
+IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false;
 
 /* imported data */
 extern HashTable dbHashtable;
@@ -143,7 +143,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void)
         return IX_ETH_DB_FAIL;
     }
 
-    ixEthDBLearningShutdown = FALSE;
+    ixEthDBLearningShutdown = false;
 
     /* create processor loop thread */
     if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
@@ -173,7 +173,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void)
 IX_ETH_DB_PUBLIC
 IxEthDBStatus ixEthDBStopLearningFunction(void)
 {
-    ixEthDBLearningShutdown = TRUE;
+    ixEthDBLearningShutdown = true;
 
     /* wake up event processing loop to actually process the shutdown event */
     ixOsalSemaphorePost(&eventQueueSemaphore);
@@ -253,13 +253,13 @@ void ixEthDBEventProcessorLoop(void *unused1)
     IxEthDBPortMap triggerPorts;
     IxEthDBPortId portIndex;
 
-    ixEthDBEventProcessorRunning = TRUE;
+    ixEthDBEventProcessorRunning = true;
 
     IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
 
     while (!ixEthDBLearningShutdown)
     {
-        BOOL keepProcessing    = TRUE;
+        BOOL keepProcessing    = true;
         UINT32 processedEvents = 0;
 
         IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
@@ -302,7 +302,7 @@ void ixEthDBEventProcessorLoop(void *unused1)
                 if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
                     || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
                 {
-                    keepProcessing = FALSE;
+                    keepProcessing = false;
                 }
             }
 
@@ -313,10 +313,10 @@ void ixEthDBEventProcessorLoop(void *unused1)
     /* turn off automatic updates */
     for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
     {
-        ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
+        ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
     }
 
-    ixEthDBEventProcessorRunning = FALSE;
+    ixEthDBEventProcessorRunning = false;
 }
 
 /**
@@ -381,7 +381,7 @@ void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
  *
  * @param macAddr MAC address of the new record
  * @param portID port ID of the new record
- * @param staticEntry TRUE if record is static, FALSE if dynamic
+ * @param staticEntry true if record is static, false if dynamic
  *
  * @return IX_ETH_DB_SUCCESS if the event creation was
  * successfull or IX_ETH_DB_BUSY if the event queue is full
@@ -430,7 +430,7 @@ IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPor
 {
     if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
     {
-        return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE);
+        return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false);
     }
     else
     {

drivers/net/npe/IxEthDBFeatures.c

@@ -169,7 +169,7 @@ void ixEthDBFeatureCapabilityScan(void)
                 /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
                 portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
                 portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = TRUE;
+                portInfo->enabled        = true;
 
 #define CONFIG_WITH_VLAN  /* test-only: VLAN support not included to save space!!! */
 #ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
@@ -195,7 +195,7 @@ void ixEthDBFeatureCapabilityScan(void)
                     ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
 
                     /* clear TTI table - no VLAN tagged frames will be transmitted */
-                    ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE);
+                    ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false);
 
                     /* set membership on 0, otherwise no Tx or Rx is working */
                     ixEthDBPortVlanMembershipAdd(portIndex, 0);
@@ -221,12 +221,12 @@ void ixEthDBFeatureCapabilityScan(void)
 #endif
 
                 /* by default we turn off invalid source MAC address filtering */
-                ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE);
+                ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false);
 
                 /* disable port, VLAN, Firewall feature bits */
                 portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
                 portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = FALSE;
+                portInfo->enabled        = false;
 
                 /* enable filtering by default if present */
                 if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
@@ -271,7 +271,7 @@ IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *
  *
  * @param portID ID of the port
  * @param feature feature to enable or disable
- * @param enabled TRUE to enable the selected feature or FALSE to disable it
+ * @param enabled true to enable the selected feature or false to disable it
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.
@@ -333,7 +333,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
     }
 
     /* force port enabled */
-    portInfo->enabled = TRUE;
+    portInfo->enabled = true;
 
     if (enable)
     {
@@ -399,7 +399,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
             /* enable TPID port extraction */
             if (status == IX_ETH_DB_SUCCESS)
             {
-                status = ixEthDBVlanPortExtractionEnable(portID, TRUE);
+                status = ixEthDBVlanPortExtractionEnable(portID, true);
             }
         }
         else if (feature == IX_ETH_DB_FIREWALL)
@@ -414,7 +414,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
 
                 if (status == IX_ETH_DB_SUCCESS)
                 {
-                    status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
+                    status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
                 }
             }
         }
@@ -445,7 +445,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
 
             if (status == IX_ETH_DB_SUCCESS)
             {
-                status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
+                status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
             }
 
             if (status == IX_ETH_DB_SUCCESS)
@@ -515,7 +515,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
             /* disable TPID port extraction */
             if (status == IX_ETH_DB_SUCCESS)
             {
-                status = ixEthDBVlanPortExtractionEnable(portID, FALSE);
+                status = ixEthDBVlanPortExtractionEnable(portID, false);
             }
         }
 #endif
@@ -538,9 +538,9 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature,
  *
  * @param portID port ID
  * @param present location to store a boolean value indicating
- * if the feature is present (TRUE) or not (FALSE)
+ * if the feature is present (true) or not (false)
  * @param enabled location to store a booleam value indicating
- * if the feature is present (TRUE) or not (FALSE)
+ * if the feature is present (true) or not (false)
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.

drivers/net/npe/IxEthDBFirewall.c

@@ -72,7 +72,7 @@ IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32
     UINT32 mode        = 0;    
     PortInfo *portInfo = &ixEthDBPortInfo[portID];
 
-    mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
+    mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
 
     FILL_SETFIREWALLMODE_MSG(message, 
         IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
@@ -123,8 +123,8 @@ IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode m
  * @brief enables or disables the invalid source MAC address filter
  *
  * @param portID ID of the port
- * @param enable TRUE to enable invalid source MAC address filtering
+ * @param enable true to enable invalid source MAC address filtering
- * or FALSE to disable it
+ * or false to disable it
  *
  * The invalid source MAC address filter will discard, when enabled,
  * frames whose source MAC address is a multicast or the broadcast MAC

drivers/net/npe/IxEthDBLearning.c

@@ -105,8 +105,8 @@ UINT32 ixEthDBKeyXORHash(void *key)
  * collisions, i.e. descriptors with different mac addresses and the same
  * hash value, where this function is used to differentiate entries.
  *
- * @retval TRUE if the entry matches the reference key (equal addresses)
+ * @retval true if the entry matches the reference key (equal addresses)
- * @retval FALSE if the entry does not match the reference key
+ * @retval false if the entry does not match the reference key
  *
  * @internal
  */

drivers/net/npe/IxEthDBNPEAdaptor.c

@@ -203,7 +203,7 @@ void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSi
         /* debug */
         IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
 
-        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE)
+        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true)
         {
             IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
         }

drivers/net/npe/IxEthDBPortUpdate.c

@@ -60,7 +60,7 @@ extern HashTable dbHashtable;
  *
  * @param typeArray array indexed on record types, each
  * element indicating whether the record type requires an
- * automatic update (TRUE) or not (FALSE)
+ * automatic update (true) or not (false)
  * 
  * Automatic updates are done for registered record types
  * upon adding, updating (that is, updating the record portID) 
@@ -70,7 +70,7 @@ extern HashTable dbHashtable;
  *
  * It is assumed that the typeArray parameter is allocated large
  * enough to hold all the user defined types. Also, the type
- * array should be initialized to FALSE as this function only
+ * array should be initialized to false as this function only
  * caters for types which do require automatic updates.
  *
  * Note that this function should be called by the component
@@ -84,8 +84,8 @@ extern HashTable dbHashtable;
 IX_ETH_DB_PUBLIC
 UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
 {
-    typeArray[IX_ETH_DB_FILTERING_RECORD]      = TRUE;
+    typeArray[IX_ETH_DB_FILTERING_RECORD]      = true;
-    typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE;
+    typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true;
 
     return 2;
 }
@@ -174,7 +174,7 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
 {
     UINT32 portIndex;
     BOOL result;
-    BOOL portsLeft = TRUE;
+    BOOL portsLeft = true;
 
     while (portsLeft)
     {
@@ -305,11 +305,11 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
             }
 
             /* mark tree as valid */
-            port->updateMethod.searchTreePendingWrite = TRUE;
+            port->updateMethod.searchTreePendingWrite = true;
         }
         else
         {
-            portsLeft = FALSE;
+            portsLeft = false;
 
             IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");            
         }
@@ -374,7 +374,7 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty
 
     /* forget last used search tree */
     port->updateMethod.searchTree             = NULL;
-    port->updateMethod.searchTreePendingWrite = FALSE;
+    port->updateMethod.searchTreePendingWrite = false;
 
     /* dependending on the update type we do different things */
     if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
@@ -393,9 +393,9 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty
         }
         else
         {
-            ixEthDBPortInfo[portID].agingEnabled                = FALSE;
+            ixEthDBPortInfo[portID].agingEnabled                = false;
-            ixEthDBPortInfo[portID].updateMethod.updateEnabled  = FALSE;
+            ixEthDBPortInfo[portID].updateMethod.updateEnabled  = false;
-            ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
+            ixEthDBPortInfo[portID].updateMethod.userControlled = true;
 
             ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
 

drivers/net/npe/IxEthDBReports.c

@@ -62,7 +62,7 @@ IX_ETH_DB_PUBLIC
 IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
 {
     UINT32 portIndex;
-    BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE;
+    BOOL mapSelf = true, mapNone = true, firstPort = true;
     
     /* dependency port maps */
     printf("Dependency port map: ");
@@ -72,22 +72,22 @@ IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap
     {
         if (IS_PORT_INCLUDED(portIndex, map))
         {
-            mapNone   = FALSE;
+            mapNone   = false;
             
             if (portIndex != portID)
             {
-                mapSelf = FALSE;
+                mapSelf = false;
             }
             
             printf("%s%d", firstPort ? "{" : ", ", portIndex);
             
-            firstPort = FALSE;
+            firstPort = false;
         }
     }
     
     if (mapNone)
     {
-        mapSelf = FALSE;
+        mapSelf = false;
     }
     
     printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");

drivers/net/npe/IxEthDBSearch.c

@@ -50,7 +50,7 @@ extern HashTable dbHashtable;
  * @param untypedReference record to match against
  * @param untypedEntry record to match
  *
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
  *
  * @internal
  */
@@ -61,7 +61,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
     MacDescriptor *reference = (MacDescriptor *) untypedReference;
     
     /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
+    if ((entry->type & reference->type) == 0) return false;
        
     return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
 }
@@ -73,7 +73,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
  * @param untypedReference record to match against
  * @param untypedEntry record to match
  *
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
  *
  * @internal
  */
@@ -84,7 +84,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
     MacDescriptor *reference = (MacDescriptor *) untypedReference;
     
     /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
+    if ((entry->type & reference->type) == 0) return false;
     
     return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
         IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
@@ -98,7 +98,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
  * @param untypedReference record to match against
  * @param untypedEntry record to match
  *
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
  *
  * @internal
  */
@@ -109,7 +109,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
     MacDescriptor *reference = (MacDescriptor *) untypedReference;
     
     /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return FALSE;
+    if ((entry->type & reference->type) == 0) return false;
     
     return (entry->portID == reference->portID) &&
         (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
@@ -125,7 +125,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
  * array on invalid types. Calling it will display an 
  * error message, indicating an error in the component logic.
  *
- * @return FALSE
+ * @return false
  *
  * @internal
  */
@@ -137,7 +137,7 @@ BOOL ixEthDBNullMatch(void *reference, void *entry)
     ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
 
 
-    return FALSE;
+    return false;
 }
 
 /**

drivers/net/npe/IxEthDBSpanningTree.c

@@ -49,7 +49,7 @@
  * @brief sets the STP blocking state of a port
  *
  * @param portID ID of the port
- * @param blocked TRUE to block the port or FALSE to unblock it
+ * @param blocked true to block the port or false to unblock it
  * 
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.

drivers/net/npe/IxEthDBUtil.c

@@ -94,13 +94,13 @@ BOOL ixEthDBCheckSingleBitValue(UINT32 value)
 	
     while (value != 0)
     {
-        if (value == 1) return TRUE;
+        if (value == 1) return true;
-        else if ((value & 1) == 1) return FALSE;
+        else if ((value & 1) == 1) return false;
 
         value >>= 1;
     }
     
-    return FALSE;
+    return false;
 
 #endif
 }

drivers/net/npe/IxEthDBVlan.c

@@ -642,7 +642,7 @@ IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet
  *
  * @param portID ID of the port
  * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled TRUE to enable and FALSE to disable tagging
+ * @param enabled true to enable and false to disable tagging
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.
@@ -670,7 +670,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEt
  * @param portID ID of the port
  * @param vlanID VLAN ID to retrieve the tagging status for
  * @param enabled location to store the tagging status
- * (TRUE - tagging enabled, FALSE - tagging disabled)
+ * (true - tagging enabled, false - tagging disabled)
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.
@@ -702,7 +702,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEt
  * @param portID ID of the port
  * @param vlanIDMin start of VLAN range
  * @param vlanIDMax end of VLAN range
- * @param enabled TRUE to enable or FALSE to disable VLAN tagging
+ * @param enabled true to enable or false to disable VLAN tagging
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.
@@ -1151,7 +1151,7 @@ IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriori
  * from the VLAN TPID field
  *
  * @param portID ID of the port
- * @param enable TRUE to enable or FALSE to disable
+ * @param enable true to enable or false to disable
  *
  * Note that this function is documented in the main component
  * header file, IxEthDB.h.

drivers/net/npe/IxEthMii.c

@@ -65,7 +65,7 @@ PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
  * Scan for PHYs on the MII bus. This function returns
  * an array of booleans, one for each PHY address.
  * If a PHY is found at a particular address, the
- * corresponding entry in the array is set to TRUE.
+ * corresponding entry in the array is set to true.
  *
  */
 
@@ -89,7 +89,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
         i<IXP425_ETH_ACC_MII_MAX_ADDR;
 	i++)
     {
-	phyPresent[i] = FALSE;
+	phyPresent[i] = false;
     }
 
     /* iterate through the PHY addresses */
@@ -119,7 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
 		    )
 		{
 		    /* supported phy */
-		    phyPresent[i] = TRUE;
+		    phyPresent[i] = true;
 		} /* end of if(ixEthMiiPhyId) */
 		else
 		{
@@ -131,7 +131,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
 				    "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", 
 				    ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
 			ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
-			phyPresent[i] = TRUE;
+			phyPresent[i] = true;
 		    }
 		} 
 	    }
@@ -347,10 +347,10 @@ ixEthMiiLinkStatus(UINT32 phyAddr,
 	return IX_FAIL;
     }
 
-    *linkUp = FALSE;
+    *linkUp = false;
-    *speed100 = FALSE;
+    *speed100 = false;
-    *fullDuplex = FALSE;
+    *fullDuplex = false;
-    *autoneg = FALSE;
+    *autoneg = false;
 
     if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
 	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
@@ -406,20 +406,20 @@ ixEthMiiLinkStatus(UINT32 phyAddr,
 		    if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
 		    {
 			/* 100 Base X full dplx */
-			*speed100 = TRUE;
+			*speed100 = true;
-			*fullDuplex = TRUE;
+			*fullDuplex = true;
 			return IX_SUCCESS;
 		    }
 		    if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
 		    {
 			/* 100 Base X half dplx */
-			*speed100 = TRUE;
+			*speed100 = true;
 			return IX_SUCCESS;
 		    }
 		    if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
 		    {
 			/* 10 mb full dplx */
-			*fullDuplex = TRUE;
+			*fullDuplex = true;
 			return IX_SUCCESS;
 		    }
 		    if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)

drivers/net/npe/IxFeatureCtrl.c

@@ -72,7 +72,7 @@ IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \
 
 
 /* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE;
+PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false;
 
 /* Pointer holding the virtual address of the Feature Control Register */
 PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
@@ -81,7 +81,7 @@ PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
 PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
 
 /* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = FALSE ;
+PRIVATE BOOL swConfigurationFlag = false ;
 
 /* Array containing component mask values */
 #ifdef __ixp42X
@@ -158,7 +158,7 @@ void ixFeatureCtrlExpMap(void)
 
     /* If the EXP Configuration space has already been mapped then
      * return */
-    if (ixFeatureCtrlExpCfgRegionMapped == TRUE)
+    if (ixFeatureCtrlExpCfgRegionMapped == true)
     {
 	return;
     }
@@ -176,7 +176,7 @@ void ixFeatureCtrlExpMap(void)
 	(VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
 
     /* Mark the fact that the EXP_CONFIG space has already been mapped */
-    ixFeatureCtrlExpCfgRegionMapped = TRUE;
+    ixFeatureCtrlExpCfgRegionMapped = true;
 }
 
 /**
@@ -186,15 +186,15 @@ void ixFeatureCtrlExpMap(void)
 PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
 {
   UINT32 i;
-  if (FALSE == swConfigurationFlag)
+  if (false == swConfigurationFlag)
   {
     for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
     {
         /* By default, all software configuration are enabled */
-        swConfiguration[i]= TRUE ;
+        swConfiguration[i]= true ;
     }
     /*Make sure this function only initializes swConfiguration[] once*/
-    swConfigurationFlag = TRUE ;
+    swConfigurationFlag = true ;
   }  
 }
 
@@ -326,7 +326,7 @@ ixFeatureCtrlProductIdRead ()
     extern  IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
     
 #ifndef IN_KERNEL
-    mode = SetKMode(TRUE);
+    mode = SetKMode(true);
 #endif
     pdId = AsmixFeatureCtrlProductIdRead();
 #ifndef IN_KERNEL
@@ -372,7 +372,7 @@ ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
   ixFeatureCtrlSwConfigurationInit();
   
   /* Check and return software configuration */
-  return  ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
+  return  ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
 }
 
 /**

drivers/net/npe/IxNpeDl.c

@@ -89,9 +89,9 @@ typedef struct
  */
 static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
 {
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
+    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
+    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
+    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
 };
 
 static IxNpeDlStats ixNpeDlStats;
@@ -99,7 +99,7 @@ static IxNpeDlStats ixNpeDlStats;
 /*
  * Software guard to prevent NPE from being started multiple times.
  */
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ;
+static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ;
 
 
 /*
@@ -195,7 +195,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
             if (IX_SUCCESS == status)
             {
                 ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = TRUE;
+                ixNpeDlNpeState[npeId].validImage = true;
                 ixNpeDlStats.successfulDownloads++;
 
                 status =  ixNpeDlNpeExecutionStart (npeId);
@@ -204,7 +204,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
                      (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
             {
                 ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = FALSE;
+                ixNpeDlNpeState[npeId].validImage = false;
                 ixNpeDlStats.criticalFailDownloads++;
             }
         } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
@@ -507,7 +507,7 @@ ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
     if (IX_SUCCESS == status)
     {
         /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = FALSE ;
+        ixNpeDlNpeStarted[npeId] = false ;
     }
 
     return status;
@@ -573,7 +573,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
         } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
     } /* end of if not IXP42x-A0 Silicon */
 
-    if (TRUE == ixNpeDlNpeStarted[npeId])
+    if (true == ixNpeDlNpeStarted[npeId])
     {
         /* NPE has been started. */
         return IX_SUCCESS ;
@@ -588,7 +588,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
     if (IX_SUCCESS == status)
     {
         /* Indicate NPE has started */
-        ixNpeDlNpeStarted[npeId] = TRUE ;
+        ixNpeDlNpeStarted[npeId] = true ;
     }
 
     IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
@@ -674,7 +674,7 @@ ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
     if (IX_SUCCESS == status)
     {
         /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = FALSE ;
+        ixNpeDlNpeStarted[npeId] = false ;
     }
 
     return status;
@@ -840,10 +840,10 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
              * currently loaded images. If a critical error occured
              * during download, record that the NPE has an invalid image
              */
-            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE);
+            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true);
             if (IX_SUCCESS == status)
             {
-                ixNpeDlNpeState[npeId].validImage = TRUE;
+                ixNpeDlNpeState[npeId].validImage = true;
                 ixNpeDlStats.successfulDownloads++;
 
                 status = ixNpeDlNpeExecutionStart (npeId);
@@ -851,7 +851,7 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
             else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
                      (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
             {
-                ixNpeDlNpeState[npeId].validImage = FALSE;
+                ixNpeDlNpeState[npeId].validImage = false;
                 ixNpeDlStats.criticalFailDownloads++;
             }
 

drivers/net/npe/IxNpeDlImageMgr.c

@@ -414,11 +414,11 @@ ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary)
 {
     IxNpeDlImageMgrImageLibraryHeader *header =
 	(IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
-    BOOL result = TRUE;
+    BOOL result = true;
 
     if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
     {
-	result = FALSE;
+	result = false;
 	ixNpeDlImageMgrStats.invalidSignature++;
     }
 
@@ -469,11 +469,11 @@ ixNpeDlImageMgrImageIdCompare (
 	(imageIdA->major   == imageIdB->major)   &&
 	(imageIdA->minor   == imageIdB->minor))
     {
-	return TRUE;
+	return true;
     }
     else
     {
-	return FALSE;
+	return false;
     }
 }
 
@@ -491,11 +491,11 @@ ixNpeDlImageMgrNpeFunctionIdCompare (
     if ((imageIdA->npeId   == imageIdB->npeId)   &&
 	(imageIdA->functionalityId == imageIdB->functionalityId))
     {
-	return TRUE;
+	return true;
     }
     else
     {
-	return FALSE;
+	return false;
     }
 }
 
@@ -550,7 +550,7 @@ ixNpeDlImageMgrImageFind_legacy (
     UINT32 imageCount = 0;   
     IX_STATUS status = IX_FAIL;
     IxNpeDlImageMgrImageLibraryHeader *header;
-    BOOL imageFound = FALSE;
+    BOOL imageFound = false;
 
     IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
 		     "Entering ixNpeDlImageMgrImageFind\n");
@@ -584,7 +584,7 @@ ixNpeDlImageMgrImageFind_legacy (
 		/* get the image size */
 		*imageSize = header->entry[imageCount].image.size;
 		status = IX_SUCCESS;
-		imageFound = TRUE;
+		imageFound = true;
 	    }
 	    imageCount++;
 	}

drivers/net/npe/IxNpeDlNpeMgr.c

@@ -229,7 +229,7 @@ static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
 static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
 
 /* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = FALSE;
+static BOOL ixNpeDlMemInitialised = false;
 
 
 /*
@@ -290,7 +290,7 @@ ixNpeDlNpeMgrInit (void)
 	IX_OSAL_ASSERT(virtAddr);
 	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
 
-	ixNpeDlMemInitialised = TRUE;
+	ixNpeDlMemInitialised = true;
     }
 }
 
@@ -314,7 +314,7 @@ ixNpeDlNpeMgrUninit (void)
     ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
     ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
 
-    ixNpeDlMemInitialised = FALSE;
+    ixNpeDlMemInitialised = false;
 
     return IX_SUCCESS;
 }
@@ -662,7 +662,7 @@ ixNpeDlNpeMgrNpeReset (
     {
 	/* for each physical register in the NPE reg file, write 0 : */
 	status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
-						0, TRUE);
+						0, true);
 	if (status != IX_SUCCESS)
 	{
 	    return status;  /* abort reset */
@@ -684,7 +684,7 @@ ixNpeDlNpeMgrNpeReset (
 	    { 
 		regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
 		status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
-						    ctxtReg, regVal, TRUE);
+						    ctxtReg, regVal, true);
 		if (status != IX_SUCCESS)
 		{
 		    return status;  /* abort reset */

drivers/net/npe/IxNpeMh.c

@@ -79,7 +79,7 @@
  * static variables.
  */
 
-PRIVATE BOOL ixNpeMhInitialized = FALSE;
+PRIVATE BOOL ixNpeMhInitialized = false;
 
 /*
  * Extern function prototypes.
@@ -128,7 +128,7 @@ PUBLIC IX_STATUS ixNpeMhInitialize (
      */
     ixNpeMhConfigInitialize (npeInterrupts);
 
-    ixNpeMhInitialized = TRUE;
+    ixNpeMhInitialized = true;
 
     IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
                      "ixNpeMhInitialize\n");
@@ -153,7 +153,7 @@ PUBLIC IX_STATUS ixNpeMhUnload (void)
     /* Uninitialize the Configuration module */
     ixNpeMhConfigUninit ();
 
-    ixNpeMhInitialized = FALSE;
+    ixNpeMhInitialized = false;
 
     IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
                      "ixNpeMhUnload\n");

drivers/net/npe/IxNpeMhConfig.c

@@ -105,7 +105,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
         0,
         0,
         NULL,
-        FALSE
+        false
     },
     {
         0,
@@ -116,7 +116,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
         0,
         0,
         NULL,
-        FALSE
+        false
     },
     {
         0,
@@ -127,7 +127,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
         0,
         0,
         NULL,
-        FALSE
+        false
     }
 };
 

drivers/net/npe/IxNpeMhSend.c

@@ -124,7 +124,7 @@ BOOL ixNpeMhSendInFifoIsFull(
     IxNpeMhNpeId npeId,
     UINT32 maxSendRetries)
 {
-    BOOL isFull = FALSE;
+    BOOL isFull = false;
     UINT32 numRetries = 0;
 
     /* check the NPE's inFIFO */

drivers/net/npe/IxOsalOsSemaphore.c

@@ -135,10 +135,10 @@ static void drv_mutex_destroy(IxOsalMutex *mutex)
 
 static int drv_mutex_trylock(IxOsalMutex *mutex)
 {
-	int result = TRUE;
+	int result = true;
 
 	if (*mutex == 1)
-		result = FALSE;
+		result = false;
 
 	return result;
 }

drivers/net/npe/IxQMgrDispatcher.c

@@ -160,7 +160,7 @@ static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES];
 /*
  * This flag indicates to the dispatcher that the priority table needs to be rebuilt.
  */
-static BOOL rebuildTable = FALSE;
+static BOOL rebuildTable = false;
 
 /* Dispatcher statistics */
 static IxQMgrDispatcherStats dispatcherStats;
@@ -197,7 +197,7 @@ ixQMgrDispatcherInit (void)
     int i;
     IxFeatureCtrlProductId productId = 0;
     IxFeatureCtrlDeviceId deviceId = 0;
-    BOOL stickyIntSilicon = TRUE; 
+    BOOL stickyIntSilicon = true;
 
     /* Set default priorities */
     for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
@@ -226,7 +226,7 @@ ixQMgrDispatcherInit (void)
 	dispatcherStats.queueStats[i].priorityChangeCnt = 0;
 	dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
 	dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
-        dispatcherStats.queueStats[i].notificationEnabled = FALSE;
+        dispatcherStats.queueStats[i].notificationEnabled = false;
         dispatcherStats.queueStats[i].srcSel = 0;
 
     }
@@ -258,7 +258,7 @@ ixQMgrDispatcherInit (void)
         (IX_FEATURE_CTRL_SILICON_TYPE_A0 == 
         (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) 
     {
-       stickyIntSilicon = FALSE;
+       stickyIntSilicon = false;
     }
 
     /*
@@ -293,7 +293,7 @@ ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
     /* Change priority */
     dispatchQInfo[qId].priority = priority;
     /* Set flag */
-    rebuildTable = TRUE;
+    rebuildTable = true;
 
     ixOsalIrqUnlock(ixQMgrLockKey);
 
@@ -364,7 +364,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId,
 #endif
 
 #ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = TRUE;
+    dispatcherStats.queueStats[qId].notificationEnabled = true;
     dispatcherStats.queueStats[qId].srcSel = srcSel;
 #endif
 
@@ -428,7 +428,7 @@ ixQMgrNotificationDisable (IxQMgrQId qId)
      * so need critical section
      */
 #ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = FALSE;
+    dispatcherStats.queueStats[qId].notificationEnabled = false;
 #endif
 
     ixQMgrLockKey = ixOsalIrqLock();
@@ -593,7 +593,7 @@ ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
 	qIndex += IX_QMGR_MIN_QUEUPP_QID;
     }
 
-    if (statusChangeFlag == FALSE)
+    if (statusChangeFlag == false)
     {
 	/* check if the interrupt register contains 
 	 * only 1 bit set (happy day scenario)
@@ -800,7 +800,7 @@ ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
              * For example:
              *                                        intRegVal = 0x0010
              *               currDispatchQInfo->intRegCheckMask = 0x0010
-             *    intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
+             *    intRegVal == currDispatchQInfo->intRegCheckMask is true.
              */
              currDispatchQInfo = &dispatchQInfo[qIndex];
              if (intRegVal == currDispatchQInfo->intRegCheckMask)
@@ -955,7 +955,7 @@ ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
         * For example:
         *                                        intRegVal = 0x0010
         *               currDispatchQInfo->intRegCheckMask = 0x0010
-        *    intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
+        *    intRegVal == currDispatchQInfo->intRegCheckMask is true.
         */
         currDispatchQInfo = &dispatchQInfo[qIndex];
         if (intRegVal == currDispatchQInfo->intRegCheckMask)
@@ -1118,7 +1118,7 @@ ixQMgrDispatcherReBuildPriorityTable (void)
     int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
 
     /* Reset the rebuild flag */
-    rebuildTable = FALSE;
+    rebuildTable = false;
 
     /* initialize the mak used to identify the queues in the first half
      * of the priority table
@@ -1266,7 +1266,7 @@ ixQMgrPeriodicDone (void)
               * Update statistics 
               */
              dispatcherStats.queueStats[i].enableCount++;
-             dispatcherStats.queueStats[i].notificationEnabled = TRUE;
+             dispatcherStats.queueStats[i].notificationEnabled = true;
 #endif
         }
     }

drivers/net/npe/IxQMgrInit.c

@@ -66,7 +66,7 @@
  * Set to true if initialized
  * N.B. global so integration/unit tests can reinitialize
  */
-BOOL qMgrIsInitialized = FALSE;
+BOOL qMgrIsInitialized = false;
 
 /*
  * Function definitions.
@@ -90,7 +90,7 @@ ixQMgrInit (void)
     ixQMgrQAccessInit ();
 
     /* Initialization complete */
-    qMgrIsInitialized = TRUE;
+    qMgrIsInitialized = true;
 
     return IX_SUCCESS;
 }
@@ -107,7 +107,7 @@ ixQMgrUnload (void)
     ixQMgrQCfgUninit ();
 
     /* Uninitialization complete */
-    qMgrIsInitialized = FALSE;
+    qMgrIsInitialized = false;
 
     return IX_SUCCESS;
 }

drivers/net/npe/IxQMgrQCfg.c

@@ -94,7 +94,7 @@ typedef struct
     char qName[IX_QMGR_MAX_QNAME_LEN+1];       /* Textual description of a queue*/
     IxQMgrQSizeInWords qSizeInWords;           /* The number of words in the queue */
     IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
-    BOOL isConfigured;                         /* This flag is TRUE if the queue has
+    BOOL isConfigured;                         /* This flag is true if the queue has
                                                 *   been configured
                                                 */
 } IxQMgrCfgQ;
@@ -120,7 +120,7 @@ static UINT32 freeSramAddress=0;
 /* 4 words of zeroed memory for inline access */
 static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
 
-static BOOL cfgInitialized = FALSE;
+static BOOL cfgInitialized = false;
 
 static IxOsalMutex ixQMgrQCfgMutex;
 
@@ -177,10 +177,10 @@ ixQMgrQCfgInit (void)
 	strcpy (cfgQueueInfo[loopIndex].qName, "");
 	cfgQueueInfo[loopIndex].qSizeInWords = 0;
 	cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
-	cfgQueueInfo[loopIndex].isConfigured = FALSE;
+	cfgQueueInfo[loopIndex].isConfigured = false;
 
 	/* Statistics */
-	stats.qStats[loopIndex].isConfigured = FALSE;
+	stats.qStats[loopIndex].isConfigured = false;
 	stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
     }
 
@@ -191,13 +191,13 @@ ixQMgrQCfgInit (void)
     
     ixOsalMutexInit(&ixQMgrQCfgMutex);
 
-    cfgInitialized = TRUE;
+    cfgInitialized = true;
 }
 
 void
 ixQMgrQCfgUninit (void)
 {
-    cfgInitialized = FALSE;
+    cfgInitialized = false;
 
     /* Uninitialise the AqmIf component */
     ixQMgrAqmIfUninit ();
@@ -281,13 +281,13 @@ ixQMgrQConfig (char *qName,
 	      IX_QMGR_QUE_BUFFER_SPACE_SIZE);
 
     /* The queue is now configured */
-    cfgQueueInfo[qId].isConfigured = TRUE;
+    cfgQueueInfo[qId].isConfigured = true;
 
     ixOsalMutexUnlock(&ixQMgrQCfgMutex);
 
 #ifndef NDEBUG
     /* Update statistics */
-    stats.qStats[qId].isConfigured = TRUE;
+    stats.qStats[qId].isConfigured = true;
     stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
 #endif
     return IX_SUCCESS;
@@ -417,7 +417,7 @@ ixQMgrQIsConfigured (IxQMgrQId qId)
 {
     if (!IX_QMGR_QID_IS_VALID(qId))
     {
-	return FALSE;
+	return false;
     }
 
     return cfgQueueInfo[qId].isConfigured;
@@ -487,7 +487,7 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
 	case IX_QMGR_Q_WM_LEVEL64:
 	    break;
 	default:
-	    return FALSE;
+	    return false;
     }
 
     /* Check watermark is not bigger than the qSizeInEntries */
@@ -495,10 +495,10 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
 
     if ((unsigned)level > qSizeInEntries)
     {
-	return FALSE;
+	return false;
     }
 
-    return TRUE;
+    return true;
 }
 
 PRIVATE BOOL
@@ -512,10 +512,10 @@ qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
 	case IX_QMGR_Q_SIZE32:
 	case IX_QMGR_Q_SIZE64:
 	case IX_QMGR_Q_SIZE128:
-	    status = TRUE;
+	    status = true;
 	    break;
 	default:
-	    status = FALSE;
+	    status = false;
 	    break;
     }
 
@@ -532,10 +532,10 @@ qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
 	case IX_QMGR_Q_ENTRY_SIZE1:
 	case IX_QMGR_Q_ENTRY_SIZE2:
 	case IX_QMGR_Q_ENTRY_SIZE4:
-	    status = TRUE;
+	    status = true;
 	    break;
 	default:
-	    status = FALSE;
+	    status = false;
 	    break;
     }
 

drivers/net/npe/include/IxAtmdAccCtrl.h

@@ -1933,12 +1933,12 @@ PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
 * @brief disable a PHY logical port
 *
 * This function indicates if the port disable for a port has completed. This
-* function will return TRUE if the port has never been enabled.
+* function will return true if the port has never been enabled.
 *
 * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
 *
-* @return @li TRUE disable is complete
+* @return @li true disable is complete
-* @return @li FALSE disable failed, wrong parameter .
+* @return @li false disable failed, wrong parameter .
 *
 * @note - This function needs internal locks and should not be called
 *         from an interrupt context